Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2003-12-30
2008-12-02
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07461313
ABSTRACT:
Apparatus and method for testing a CDMA integrated circuit including a demodulator for correlating input data with one of a set of codes and a test data pattern generator for spreading input test data with one of the set of codes to form a spread test data and providing the spread test data to the demodulator. The set of codes may be combined with the input test data to generate a set of spread test data which are then fed to the various components of the CDMA chip for testing the various components. In one embodiment, each one of the set of codes comprises a scrambling code and a spreading code.
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Rahul Chauhan, CDMA HUB (http://www.geocities.com/rahulscdmapage/cdma.htm?200620 , Copyright 2002).
International Search Report-PCT/US04/043230, International Search Authority-US, Jul. 21, 2005.
Louis-Jacques Jacques
Pauley Nicholas J.
QUALCOMM Incorporated
Radosevich Steven D
Rouse Thomas R.
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