Test pattern generating method and test pattern generating syste

Details Test pattern generating method and test pattern generating syste Test pattern generating method and test pattern generating syste

1996-11-18

1999-11-30

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714 25, G06F 1100

Patent

active

059961015

ABSTRACT:
A test pattern generating method for a logical circuit comprises selecting failures to be detected in the logical circuit on which a test pattern is generated, selecting a target failure from all failures selected, generating a test pattern for detecting the target failure, performing a failure simulation on all selected failures by the generated test pattern, selecting the target failure from the failures not detected by the test pattern, and deleting a redundancy test pattern, which has a low failure detection rate, from the test patterns for detecting all failures.

REFERENCES:
patent: 5257268 (1993-10-01), Agrawal et al.
patent: 5291495 (1994-03-01), Udell, Jr.
patent: 5390193 (1995-02-01), Millman et al.
patent: 5410552 (1995-04-01), Hosokawa
patent: 5588008 (1996-12-01), Nakata
patent: 5648975 (1997-07-01), Deguchi

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