Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-10
2004-07-27
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C710S023000
Reexamination Certificate
active
06769083
ABSTRACT:
This patent application claims priority based on Japanese patent applications, H10-319637 filed on Nov. 10, 1998, and H11-310748 filed on Nov. 1, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test device, a test pattern generator for generating test patterns and a method of generating a plurality of test patterns for testing an electrical device.
2. Description of the Related Art
A conventional test pattern generator of a testing device for an electrical device comprises a SRAM or a DRAM having a large capacity to store programs for generating test patterns. The DRAM is used when the capacity of the SRAM is not enough to store necessary programs to generate the test patterns. When the DRAM is used, a test pattern is generated from the DRAM via a cache memory, because the DRAM needs to be refreshed at a predetermined period and there is inconvenient when an address of a different ROW is accessed in using the DRAM.
FIG. 1
is a block diagram of a conventional test pattern generator comprising an SRAM. The conventional test pattern generator comprises a sequence controller
62
and a pattern signal generator
26
. The sequence controller
62
comprises a vector memory
12
, vector memory banks
16
and
18
, a vector instruction multiplexer
20
and an address expander
22
. The pattern signal generator
26
comprises a pattern memory using the SRAM. The sequence controller
62
generates address signal
24
in a desired order. When the address signal
24
is successively input to the pattern signal generator
26
, each of the memory addresses stored in the pattern signal generator
26
are linked with each of the test patterns, to produce a desired series of test patterns. Thus the test patterns are generated.
The read out controller
14
of the sequence controller
62
reads out the vector instructions stored in the vector memory
12
. The vector instructions are temporarily stored in the vector memory banks
16
and
18
. The vector instruction multiplexer
20
selects a vector instruction from among the vector instructions temporarily stored in the vector memory banks
16
and
18
, and outputs the selected vector instruction to the address expander
22
. The address of the address signal
24
is expanded by the address expander
22
and transferred to the pattern signal generator
26
. Each of the pattern signals stored in the pattern memory is linked with each of the address signal
24
in the pattern signal generator
26
to generate test pattern signals
28
for testing an electrical device.
FIG. 2
shows an example of a pattern program to be stored in the vector memory
12
. The instruction “GOSUB A” means that the routine should go to the sub routine labeled “A”. The instruction “RETURN” means that the sub routine should be terminated and the routine should return to the next instruction (at an address one address added to the previous address) of the instruction “GOSUB”. The instruction “REPEAT n” means that the test pattern of the indicated address should be output n times. The instruction “NEXT” means that the routine should go to the next address (one address added to the previous address). The instruction “STOP” means that the test should be terminated.
The test patterns for an electrical device are generated by arranging each of the individual test patterns determined by these vector instructions. The instructions of the addresses #
11
to address #
15
are labeled “A”, and function as the sub routines.
FIG. 3
shows an example of a compressed pattern program to be stored in the vector memory. The pattern program of the vector instructions shown in
FIG. 2
comprises the instructions “NEXT” which means that the routine should go to the next address. Therefore, the instructions “NEXT” are omitted and the pattern program is compressed, as show in
FIG. 3
, to be stored in the vector memory. In this application, the instructions “NEXT” are omitted and the pattern program is compressed as a whole. The result is that a small capacity vector memory can serve as the test pattern generator.
The instruction “GOSUB A #
0
#
11
” means that the instruction of the address #
0
is “GOSUB A” and the address to which the routine should go is #
11
. The instruction “REPEAT
3
#
3
” means that the instruction of the address #
3
is “REPEAT
3
”, so the instruction of the address #
3
should be repeated three times. This also means that the instructions of the address #
1
and the address #
2
are “NEXT”. Thus, the pattern program is compressed as a whole.
FIG. 4
shows instructions to be stored in the pattern signal generator
26
. Predetermined patterns shown as PAT
0
, PAT
1
, . . . , PATn are previously stored in an external storage device such as a hard disk, not shown in the drawings. The predetermined patterns are then read out from the hard disk when the device is switched on, and stored in the respective addresses #
0
, #
1
, . . . , #n of the pattern signal generator
26
.
FIG. 5
shows the operation of a conventional test pattern generator. In
FIG. 5
, each of the vector memory banks
16
and
18
store three words. The pattern generator
60
is initialized before the test is started. At the initialization, the vector instructions are read out from the vector memory
12
having been previously stored in the vector memory bank
16
, based on the instructions from the read out controller
14
shown in FIG.
1
.
The read out controller
14
shown in
FIG. 1
outputs the instructions stored in the vector memory
12
to the vector memory bank
16
, taking the sequences into consideration. For example, the instruction “GOSUB A” means that the routine should go to the sub routine labeled “A”, therefore the instruction “REPEAT
2
#
13
” is written next to the instruction “GOSUB A #
0
#
11
”.
When the instruction “RPEAT” is output, the routine goes to the next address. The instruction “RETURN #
15
#
1
” is written next to the instruction “REPEAT”. The initialization is completed when the first three words are written in the vector memory bank
16
. The test is started when the initialization of the test pattern generator
60
is completed. The test proceeds as explained in the following. The address expander
14
shown in
FIG. 1
expands the compressed instructions that were stored in the vector memory bank
16
, while the test pattern generator
60
is initialized.
The address signal
24
comprising the pattern memory using SRAM is supplied to the pattern former
26
. The pattern former
26
outputs the test patterns stored therein based on the address signal
24
and applies the output test pattern signals to the electrical device
76
. After the test is started, the vector instruction multiplexer
20
selectively outputs to the address expander
22
the compressed instructions from the vector memory banks in which the vector instructions were previously stored,
A program comprising the three words stored in the vector memory bank
16
executes the instructions shown below at the initialization. Firstly, the routine goes to the address #
11
from the address #
0
by the instruction “GOSUB A #
0
, #
11
”. The routine then goes from the address #
11
to the address #
13
in order, and the address #
13
is repeated twice by the instruction “REPEAT
2
#
13
”. The routine then proceeds to the address #
14
. The routine proceeds from the address #
14
to the address #
15
, and goes to the address #
1
by the instruction “RETURN #
15
#
1
”.
While the test patterns are generated by the vector memory bank
16
, the vector instruction to be executed next is transferred from the vector memory
12
to the vector memory bank
18
based on the instructions from the read out controller
14
. After the test patterns are generated by the vector memory bank
16
, another series of test patterns are generated based on the instructions stored in the ve
Tsuto Masaru
Yamada Tatsuya
Advantest Corporation
Rosenthal & Osha L.L.P.
Tu Christine T.
LandOfFree
Test pattern generator, a testing device, and a method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test pattern generator, a testing device, and a method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test pattern generator, a testing device, and a method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3246163