Test pattern generation apparatus and method for SDRAM

Details Test pattern generation apparatus and method for SDRAM Test pattern generation apparatus and method for SDRAM

1998-07-24

2000-07-25

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714742, 714743, 714718, G01R 3128

Patent

active

060947381

ABSTRACT:
A test pattern generation apparatus and method for an SDRAM can easily generate a test pattern for a synchronous dynamic RAM (SDRAM) by having a specific wrap conversion circuit or an address conversion method. The wrap conversion circuit is provided to receive two types of address data from a pattern generator and converts the data through a specified logic circuit information. The test pattern generation method for the SDRAM is carried out by inputting column address data and wrap address data, and by generating output data which has been converted by a predetermined logic equation. The test pattern generation apparatus and method can also include an address inversion scramble for the converted output.

REFERENCES:
patent: 5854801 (1998-12-01), Yamada et al.

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