Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-02-20
2000-05-23
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714726, 714727, G01R 3128
Patent
active
060676515
ABSTRACT:
A method is provided for generating a compacted set of test sequences for use by a tester that tests an integrated circuit having a scan register containing a plurality of bits that define test inputs for the integrated circuit. In accordance with the preferred embodiment, the method begins by defining a list of faults for the integrated circuit and generates a first test sequence that defines values for those inputs necessary (preferably only those inputs necessary) to detect a target fault selected from the list of faults. The method then adds the first test sequence to a list of test sequences and marks the selected fault as detected. The method then generates an additional test sequence that defines values for those inputs necessary (preferably only those inputs necessary) to detect a target fault selected from the list of faults, a fault other than one previously marked as detected. Finally, the preferred method determines whether the additional test sequence may be compacted with any test sequence in the list of test sequences, and if so, compacts the additional test sequence with a test sequence in the set of test sequences. If the additional test sequence may not be compacted with any test sequence in the list of test sequences, the method adds the additional test sequence to the set of test sequences. The process of generating additional test sequences and compacting them, when possible, to sequences in the set of sequences is repeated until a compacted condition is reached.
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Rearick Jeffrey R.
Rohrbaugh John G.
Cady Albert De
Hewlett--Packard Company
Lamarre Guy
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