Test pattern generator and test pattern generation

Details Test pattern generator and test pattern generation Test pattern generator and test pattern generation

2005-01-18

2005-01-18

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000, C714S819000, C714S033000, C703S022000

Reexamination Certificate

active

06845480

ABSTRACT:
A test pattern generator and a method of generating a test pattern. The method includes converting a test pattern into a program and simulating the program to produce a test pattern. The test pattern is applied to a test circuit to obtain simulated test results. The program is written to a memory unit. The test circuit is tested using the program inside the memory unit to produce actual test results. The simulated test results and the actual test results are compared. If the simulated and the actual results match each other, the test circuit is repeatedly test using the test pattern until no delay between loop backs is found. However, if there is a mismatch between the simulated and the actual results, the program is adjusted and the test circuit re-tested until a match between the simulated results and the actual results is found.

REFERENCES:
patent: 6073263 (2000-06-01), Arkin et al.
patent: 6226765 (2001-05-01), Le et al.
patent: 20020038439 (2002-03-01), Sato
patent: 20020144197 (2002-10-01), Jain et al.

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