Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-08-16
2011-08-16
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000
Reexamination Certificate
active
08001437
ABSTRACT:
A test pattern generation method for determining if a combinational portion17is defective, by applying test patterns to a semiconductor integrated circuit10and comparing responses to the test patterns with expected responses, the method including: a first step of generating test patterns having logic bits for detecting defects and unspecified bits; a second step of selecting critical paths19, 19a, 19bgenerated by the application of the test patterns; a third step of identifying critical gates on the critical paths19, 19a, 19b; and a fourth step of determining unspecified bits so that a critical capture transition metric, which indicates the number of the critical gates whose states are changed, is reduced; wherein by reducing the critical capture transition metric, output delays from the critical paths19, 19a, 19bare prevented, and thereby false testing can be avoided.
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Kajihara Seiji
Miyase Kohei
Wen Xiaoqing
Chung Phung M
Kyushu Institute of Technology
Westerman Hattori Daniels & Adrian LLP
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