Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-01-04
2002-10-22
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S741000
Reexamination Certificate
active
06470468
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a test pattern generator used at the time of developing an LSI, a loop disconnecting method, a propagation path disconnecting method, a delay fault detecting method, and a computer-readable recording medium recorded with a program for making the computer execute these methods. More particularly, this invention relates to a test pattern generator for detecting a stack fault or a delay fault by a scan test method, a loop disconnecting method, a propagation path disconnecting method, a delay fault detecting method, and a computer-readable recording medium recorded with a program for making the computer execute these methods.
BACKGROUND OF THE INVENTION
In recent years, in order to effectively achieve a high reliability of an LSI, a test-facilitating design has been provided and there have been carried out detection of a stack fault or a delay fault by using a test pattern automatic generating tool (an ATPG tool) based on a scan test method. In testing a stack fault of an LSI, when there is a loop portion within the LSI to be tested, it is necessary to disconnect this loop. Further, in detecting a delay fault, it has been required to use a clock signal of an active operation frequency (at-speed) for the test.
As a prior-art test pattern generator, there is available an ATPG tool for carrying out a test by automatically disconnecting a loop and by using a clock signal of at-speed. The loop disconnecting method according the prior-art ATPG tool for detecting a stack fault will be explained at first.
FIG. 12
is a circuit diagram that shows an example of a prior-art circuit in an LSI having a loop portion, and
FIG. 13
explains a prior-art method of disconnecting the loop existing within the LSI.
Assume, for example, that within the LSI to be tested, there exists a loop circuit with a two-input AND element
51
, a two-input OR element
52
, input terminals
53
and
56
, and output terminals
54
and
55
, as shown in FIG.
12
. In the case of detecting a stack fault, the input terminal
53
or the input terminal
56
is fixed at a value of “0” or “1” (a logic value of 0 and 1), according to a condition of constraint describing a condition for satisfying a test design rule. According to the prior-art ATPG tool, regardless of whether the value of the input terminal
53
is fixed at “0” or the value of the input terminal
56
is fixed at “1”, a position of disconnection is determined and a loop is disconnected, and the value of a disconnection end
57
after the disconnection is fixed at “X (0 or 1)”.
Next, a method of detecting a delay fault using a prior-art clock signal of at-speed will be explained.
FIG. 14
shows an example of a prior-art scan test circuit for detecting a delay fault. It is assumed that a delay fault is to be detected in a scan test circuit with scan flip-flops (SFF)
61
and
62
, inverter elements
63
and
64
, an AND element
65
, and OR elements
66
and
67
, as shown in
FIG. 14
, for example. A propagation path from a Q terminal of the SFF
61
through the inverter element
653
, the AND element
65
, and the OR element
66
to a D terminal of the SFF
62
forms a combination circuit to be tested.
FIG. 15
is a timing chart for showing the operation of detecting a delay fault in the prior-art scan test circuit. In the operation of detecting a delay fault in the prior-art scan test circuit, a system clock at-speed (scan clock) is used. A scan operation is switched to a system operation by a change in data
74
at a scan-enable terminal (SM terminal) (not shown) of the SFFs
61
and
62
. In
FIG. 15
,
71
designates a period of a scan operation, and
72
and
73
designate periods (N−1 period, N period) during which the scan operation has been switched to the system operation. Data set in the SFF
61
in the test-period width passes through the combination circuit to be tested and is propagated to the SFF
62
. Based on this propagation, it is determined whether the data has been collected correctly in the period
73
, to detect a delay fault.
According to the above-described prior-art technique, in the case of detecting a stack fault, regardless of whether the value of the input terminal
53
is fixed at “0” or the value of the input terminal
56
is fixed at “1”, a position of disconnection is determined and a loop is disconnected, and the value of the disconnection end
57
is fixed at “X”. Therefore, the loop is not necessarily disconnected at an optimum position where a fault detection rate is improved. The loop may be disconnected at a position where the fault detection rate is lower. Thus, there has been a problem that it is not possible to carry out a suitable test.
Further, in the case of detecting a delay fault, the test is carried out by using a clock of at-speed. Therefore, there has been a problem that it is not possible to detect a delay fault in a path where the delay exceeds the test period of at-speed, and that the fault detection rate is lowered, so that it is not possible to carry out a suitable test. In this case, it is considered possible to insert a flip-flop (FF) or a D latch by manually disconnecting a path so that data can be propagated between the two SFFs during a test period of at-speed. However, in this case, there is no guarantee that the path is disconnected at a suitable position where the fault detection rate increases. Further, as the number of paths to be disconnected increases substantially, it has been practically impossible to manually disconnect the path.
SUMMARY OF THE INVENTION
In the light of the above-described problems, it is an object of the present invention to provide a test pattern generator, a loop disconnecting method, a propagation path disconnecting method and, a delay fault detecting method, increasing fault detection rate and capable of carrying out a suitable test, and a computer-readable recording medium recorded with a program for making the computer execute these methods.
According to a first aspect of this invention, a disconnecting unit automatically disconnects a loop portion of the integrated circuit at an optimum position where the fault detection rate is not lowered, based on the circuit structure information and three condition of constraint. Thus, it is possible to optimize the position where the loop is disconnected.
Further, the disconnecting unit automatically disconnects a disconnection end at a value which does not lower the fault detection rate, based on the circuit structure information and the condition of constraint. Thus, it is possible to optimize the position where the loop is disconnected and to optimize the value of disconnection, as well.
According to a second aspect of this invention, a disconnecting unit automatically disconnects a propagation path having a delay exceeding a test period at an optimum position where the delay is accommodated within the test period so that the fault detection rate is not lowered, based on the circuit structure information, the condition of constraint and the delay information. Thus, it is possible to optimize the position where the propagation path is disconnected so that it becomes possible to detect a delay fault of the propagation path having a delay exceeding the test period of the frequency of the actual operation.
Further, the disconnecting unit automatically sets a disconnection end at a value which does not lower a fault detection rate, based on the circuit structure information, the condition of constraint and the delay information. Thus, it is possible to optimize the position where the propagation path is disconnected and, to optimize the value for the disconnection, as well.
According to a third aspect of this invention, a generating unit applies a data take-in clock to the propagation path by at least two times and generate a pattern for observing a value taken in by the clock according to the delay information of the propagation path. Thus, it becomes possible to detect a delay fault of a propagation path having a delay exceeding the test period of the frequency of
De'cady Albert
Harris Cynthia
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
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