Test pin gating for dynamic optimization

Details Test pin gating for dynamic optimization Test pin gating for dynamic optimization

2009-09-14

2011-12-13

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

08078926

ABSTRACT:
An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.

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