Test patterns to insure read signal integrity for high speed...

Details Test patterns to insure read signal integrity for high speed... Test patterns to insure read signal integrity for high speed...

2008-05-06

2008-05-06

Chung, Phung M. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S738000, C365S201000

Reexamination Certificate

active

11314258

ABSTRACT:
A test method and implementation is described to test an internal data path within a DDR DRAM during a read operation. A worse case test sequence and a compliment of the worse case test sequence is stored within memory. The test sequence and its compliment are arranged within a data word such that upon read out of the data word, the test sequences or the compliment of the test sequences is applied to a plurality of wire connections of the internal data path. Each test sequence comprises a plurality of logical bits of the same value followed by a bit of the opposite value, which tests for charge buildup on each element of the internal data path. Adjacent elements of the internal data path connect test sequences that are compliments to maximize voltage differentials and enhance possibility of signal coupling between wire elements of the internal data path.

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