Test pattern generator

Details Test pattern generator Test pattern generator

1998-08-31

2000-02-29

Nguyen, Hoa

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714720, 714742, G11C 2900, G01R 3128

Patent

active

060322756

ABSTRACT:
It is to provide a test pattern generator that can easily generate expected value data for arbitrary initial values when testing a memory device having a function of write enable/disable control per bit. The pattern generator includes an XOR controller (131) which generates a control signal in response to instructions from an instruction memory (112), an AND gate which receives an output signal of the XOR controller (131) at its one terminal and an inverted output signal of a data generator B (15) at its other input terminal, and an exclusive OR gate (121) which receives an output of the AND gate (123) at its one input terminal and an output a data generator A (14) at the other input terminal.

REFERENCES:
patent: 4670879 (1987-06-01), Okino
patent: 4862460 (1989-08-01), Yamaguchi
patent: 4876685 (1989-10-01), Rich
patent: 5668819 (1997-09-01), Fukushima
patent: 5673271 (1997-09-01), Ohsawa
patent: 5751738 (1998-05-01), Shimura

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