Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-10-15
2002-11-19
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C714S718000, C714S719000, C714S720000
Reexamination Certificate
active
06484282
ABSTRACT:
This patent application claims priority based on a Japanese patent application, H10-295157 filed on Oct. 16, 1998, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory testing device, and more particularly to a memory testing device, a high speed test pattern generator, and a method of generating a plurality of high speed test patterns.
2. Description of the Related Art
The conventional semiconductor memory testing device is shown in FIG.
1
. The conventional semiconductor memory testing device comprises a sequence controller
62
and a pattern former
26
. The sequence controller
62
controls the generating order of the test patterns for testing a semiconductor memory device. The sequence controller
62
generates an address signal
102
to be output to the pattern generator
26
. The pattern generator
26
generates an address pattern signal
106
, a data pattern signal
108
, and a read write pattern signal
110
. The address pattern
106
is input to address input pins of the memory device. The data pattern signal
108
is a data to be written on the memory device. The read and write pattern signal
110
assigns either a write cycle in which the data of the data pattern signal
108
is written on the memory device, or a read cycle in which the data written on the memory device is read out and compared with an expected signal, which is same as the data pattern signal
108
.
The sequence controller
62
comprises a vector memory for storing vector instructions which indicate the generating order of the test patterns, a read out controller
14
for reading out the vector instructions from the vector memory
12
, a vector cache memory including bank memories
16
A and
16
C, a pattern multiplexer for selecting either of the bank memories
16
A and
16
C to output the instructions, and an address expander
22
for generating the address signal
102
based on the instructions input from the pattern multiplexer
20
. When the vector instructions read out from the vector memory
12
are being stored into one of the bank memories
16
A and
16
C, the vector instructions stored in the other of the bank memories
16
A and
16
C are read out and input to the address expander
22
via the pattern multiplexer
20
.
The pattern former
26
comprises a control memory
32
for storing a pattern program to generate each of the test patterns, and a test pattern calculator
36
for generating the test patterns based on the pattern program stored in the control memory
32
. The control memory
32
comprises an address control memory
32
a
, a data control memory
32
b
and a read and write control memory
32
c
. The test pattern calculator
36
comprises an XB register for generating an address pattern signal
106
, a TP register for generating a data pattern signal
108
, a multiplexer, and an XOR circuit. The address signal
102
generated by the sequence controller
62
is input to the address control memory
32
a
, the data control memory
32
b
, and the read and write control memory
32
c.
The test pattern calculator
36
generates the address pattern signal
106
, the data pattern signal
108
, and a read and write signal
110
based on the address signal
102
and the pattern signal stored in the control memory
32
c
. The pattern signal
106
is calculated based on the instructions read out from the address control memory
32
a
. The data pattern signal
108
is calculated based on the instructions read out from the data control memory
32
b
and the read and write control memory
32
c
. The instructions read out from the read and write control memory
32
c
are directly output as the read and write pattern signal
110
.
FIG. 2
shows instructions stored in the address control memory
32
a
, the data control memory
32
b
, and the read and write control memory
32
c
of the control memory
32
. The instruction shown as “XB<0” indicates that the value of the XB register will be zero in the next cycle. The instruction shown as “XB<XB+1” indicates that the value of the XB register increases by 1 in the next cycle. The instruction shown as “XB<XB” indicates that the value of the XB register does not change in the next cycle. The instruction shown as “TP<0” indicates that the value of the TP register will be zero in the next cycle. The instruction shown as “TP<TP” indicates that the value of the TP register does not change in the next cycle. The instruction shown as “TP</TP” indicates that the value of the TP register is inverted in the next cycle. The instruction shown as “R” indicates that the read pattern signal is generated in the current cycle, and the instruction shown as “W” indicates that the write pattern signal is generated in the current cycle. The instruction shown as “/D” indicates that the pattern signal is inverted for output in the current cycle.
For example, when the value of the address signal
102
input to the pattern former
26
is #0, the instruction read out from the address control memory
32
a
to the test pattern calculator
36
is “XB<0”, and the instruction read out from the data control memory
32
b
to the test pattern calculator
36
is “TP<0”. When the value of the address signal
102
input to the pattern former
26
is #1, the instruction read out from the address control memory
32
a
to the test pattern calculator
36
is “XB<XB+1”. In this case the instruction read out from the data control memory
32
b
to the test pattern calculator
36
is “TP<TP” and the instruction read out from the read and write control memory
32
c
to the test pattern calculator
36
is “W”. The test pattern calculator
36
generates the address pattern signal
106
, the data pattern signal
108
, and the read and write pattern signal
110
based on the instructions input.
FIG. 3
shows an example of the sequence control instruction stored in the address expander used for generating the address signal
102
. The instruction “NEXT” of the address #
0
indicates that the instruction of the next address, the address #
1
in this case, should be output. The instruction “REPEAT” indicates that the instruction of the current address should be repeatedly output “n” times, and following this the instruction of the next address should be output. The instruction “JNI A n” indicates that the instruction of the address marked with a label “A” should be output “n” times, and then the data of the next address should be output. In the example shown in
FIG. 3
, the address #
3
includes the instruction “JNI A 2”, and the address #
2
is marked with a label “A”. The data from the address #
2
is output twice at the address #
3
, and then the data. from the address #
4
is output. The instruction “STOP” indicates that the test should be terminated. The address expander generates the address signal
102
in accordance with these sequence control instructions to be output to the pattern former
26
.
FIG. 4
shows compressed instructions stored in the vector memory
12
. The sequence control instructions are extremely large in practical usage, so high speed memory with a large capacity. is required to store all of the sequence control instructions. Therefore, the sequence control instructions shown in
FIG. 3
are compressed for storage in the vector memory
12
in order to save the capacity of the memory. The compressed instructions shown in
FIG. 4
are the same as the sequence control instructions shown in FIG.
3
. The sequence control instruction “NEXT” shown in
FIG. 3
is omitted and the remainder of the sequence control instructions are stored in the vector memory
12
with each address of the instruction written next to the respective instruction.
The compressed instruction “REPEAT 4 #1” stored in the vector memory address #
0
of the vector memory
12
indicates that the sequence control instruction of the address #
1
is “REPEAT 4”. The compressed instruction “JNI 2 #3 #2” s
Advantest Corporation
Moise Emmanuel L.
Rosenthal & Osha L.L.P.
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