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Scan cell circuit and scan chain consisting of same for test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan cells with minimized shoot-through and scan chains and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain architecture for increased diagnostic capability...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain cell with delay testing capability

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain circuit and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain connectivity

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain design using skewed clocks

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain diagnostics using logic paths

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain disable function for power saving

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain extracting method, test apparatus, circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain fail diagnostics

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain partition for reducing power in shift mode

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain partition for reducing power in shift mode

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain registers that utilize feedback paths within...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan chain testing of integrated circuits with hard-cores

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan circuit low power adapter with counter

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan circuitry controlled switch connecting buffer output to...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan circuits formed peripheral of core circuits with...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan clock circuit and method therefor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan control method, scan control circuit and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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