Scan chain testing of integrated circuits with hard-cores

Details Scan chain testing of integrated circuits with hard-cores Scan chain testing of integrated circuits with hard-cores

2005-05-31

2005-05-31

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000

Reexamination Certificate

active

06901544

ABSTRACT:
The invention relates to an integrated circuit including a hard-core and a peripheral circuit. The hard-core and the peripheral circuit each include respective registers, which are couplable for scan chain testing by respective scan chain paths within the core and within the peripheral circuit. In order to avoid timing problems between the two scan chain paths, a lock-up latch is provided within the hard-core. The lock-up latch has an input coupled to the last register in the scan chain path within the hard-core, and an output coupled to the first register in the scan chain path in the peripheral circuit. The lock-up latch forms part of the hard-core and is clocked by the same clock signal as the last register in the hard-core scan chain path.

REFERENCES:
patent: 4893072 (1990-01-01), Matsumoto
patent: 5642362 (1997-06-01), Savir
patent: 5828579 (1998-10-01), Beausang
patent: 6381719 (2002-04-01), Scheck
patent: 6446229 (2002-09-01), Merrick et al.
patent: 6539497 (2003-03-01), Swoboda et al.

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