Scan circuit low power adapter with counter

Details Scan circuit low power adapter with counter Scan circuit low power adapter with counter

2001-03-09

2004-07-27

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

06769080

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
2. Description of the Related Art
FIG. 1
illustrates a conventional scan architecture that a circuit
100
can be configured into during test. In the normal functional configuration, circuit
100
may be a functional circuit within IC, but in test configuration it appears as shown in FIG.
1
. Scan architectures can be applied at various circuit levels. For example, the scan architecture of
FIG. 1
may represent the testing of a complete IC, or it may represent the testing of an embedded intellectual property core sub-circuit within an IC, such as a DSP or CPU core sub-circuit. The scan architecture includes a scan path circuit
104
, logic circuitry to be tested
108
, and connection paths
112
-
120
to a tester
110
. Tester
110
operates to: (1) output control to operate scan path
104
via control path
114
; (2) output serial test stimulus patterns to scan path
104
via scan input path
118
; (3) input serial test response patterns from scan path
104
via scan output path
120
; (4) output parallel test stimulus patterns to logic
108
via primary input path
112
; and (5) input parallel test response patterns from logic
108
via primary output path
116
. Scan path
104
operates, in addition to its scan input and scan output modes to tester
110
, to output parallel test stimulus patterns to logic
108
via path
122
, and input parallel response patterns from logic
108
via path
124
.
Typically tester
110
is interfaced to the scan architecture by probing the die pads at wafer level, or by contacting package pins after the die is assembled into a package. While tester
110
connections to the primary inputs
112
and primary outputs
116
of logic
108
are shown, the primary input and output connections could be achieved by augmentation of scan path
104
. For example, scan path
104
could be lengthened to include boundary scan cells located on each primary input and primary output of logic
108
. The boundary scan cells would provide primary inputs to and primary outputs from logic
108
, via widened stimulus and response busses
122
and
124
, respectively. In some instances, logic
108
may be sufficiently tested by scan path
104
such that it is not necessary to provide primary inputs to and outputs from logic
108
via the tester or via the above described augmentation of scan path
104
. For example, if the amount of logic
108
circuitry made testable by the use of scan path
104
in combination with the primary inputs and outputs is very small compared to the amount of logic
108
circuitry made testable by the scan path
104
alone, then the primary input and output connections to logic
108
may removed without significantly effecting the test of logic circuitry
108
. To simplify the description of the prior art and following description of the present invention, it will be assumed that logic circuit
108
is sufficiently tested using only scan path
104
, i.e. the primary inputs
112
and primary outputs
116
are not required. However, it is clear that primary input and output connections to the tester or to an augmented scan path
104
, as described above, could be used as well.
FIG. 2
illustrates an example of a conventional scan cell that could be used in scan path
104
. (Note: The optional scan cell multiplexer
218
and connection paths
220
and
224
, shown in dotted line, will not be discussed at this time, but will be discussed later in regard to
FIG. 7.
) The scan cell consists of a D-FF
204
and a multiplexer
202
. During normal configuration of the circuit
100
, multiplexer
202
and D-FF
204
receive control inputs SCANENA
210
and SCANCK
212
to input functional data from logic
108
via path
206
and output functional data via path
216
. In the normal configuration, the SCANCK to D-FF
204
is typically a functional clock, and the SCANENA signal is set such that the D-FF always clocks in functional data from logic
108
via path
206
. During the test configuration of
FIG. 2
, multiplexer
202
and D-FF
204
receive control inputs SCANENA
210
and SCANCK
212
to capture test response data from logic
108
via path
206
, shift data from scan input path
208
to scan output path
214
, and apply test stimulus data to logic
108
via path
216
. In the test configuration, the SCANCK to D-FF
204
is the test clock and the SCANENA signal is operated to allow capturing of response data from logic
108
and shifting of data from scan input
208
to scan output
214
. During test configuration, SCANENA is controlled by tester
110
via path
114
. SCANCK may also be controlled by the tester, or it may be controlled by another source, for example a functional clock source. For the purpose of simplifying the operational description, it will be assumed that the SCANCK is controlled by the tester.
The scan inputs
208
and scan outputs
214
of multiple scan cells are connected to form the serial scan path
104
. The stimulus path
216
and response path
206
of multiple scan cells in scan path
104
form the stimulus bussing path
122
and response bussing path
124
, respectively, between scan path
104
and logic
108
. From this scan cell description, it is seen that the D-FF is shared between being used in the normal functional configuration and the test configuration. During scan operations through scan path
104
, the stimulus outputs
216
from each scan cell ripple, since the stimulus
216
path is connected to the scan output path
214
. This ripple causes all the inputs to logic
108
to actively change state during scan operations. Rippling the inputs to logic
108
causes power to be consumed by the interconnect and gating capacitance in logic
108
.
FIG. 3
illustrates a simplified example of how tester
110
operates, in states
300
, the scan architecture during test. Initially the tester will output control on path
114
to place the scan architecture in an idle state
302
. Next, the tester outputs control on path
114
to place the scan architecture in an operate scan path state
304
. In the operate scan path state, the tester outputs control to cause the scan path to accept stimulus data from the tester via path
118
and to output response data to the tester via path
120
. The tester maintains the operate scan path state until the scan path has been filled with stimulus data and emptied of response data. From the operate scan path state, the tester outputs control on path
114
to place the scan architecture in a capture response data state
306
. In the capture response data state, the tester outputs control to cause the scan path to load response data from logic
108
via path
124
. From the capture response data state
306
, the tester outputs control on path
114
to cause the scan architecture to re-enter the operate scan path state
302
. The process of entering the operate scan path state
304
to load stimulus into the scan path and empty response from the scan path, and then passing through the capture response state
306
to load new response data from logic
108
repeats until the end of test. At the end of test

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