Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-04-05
2005-04-05
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06877123
ABSTRACT:
Embodiments of the present invention relate generally to scan clock waveform generation. One embodiment utilizes global and local circular shift registers to provide a series of shift/capture pulses at a manageable frequency for the tester and launch pulses that are phase shifted in order to provide for at-speed testing. Therefore, scan test patterns may be shifted in or out of state elements at lower frequencies as compared to the normal operating frequency of the integrated circuit being tested, while still allowing for at-speed testing. An alternate embodiment utilizes a circular shift register in combination with static storage devices and waveform generators to provide the shift/capture pulses and launch pulses. Embodiments of the present invention also allow for clock inversion where the clock and clock bar signals are dependent during normal mode and independent during scan test mode.
REFERENCES:
patent: 5018144 (1991-05-01), Corr et al.
patent: 5181191 (1993-01-01), Farwell
patent: 5524114 (1996-06-01), Peng
patent: 5617426 (1997-04-01), Koenemann et al.
patent: 5774474 (1998-06-01), Narayanan et al.
patent: 6014763 (2000-01-01), Dhong et al.
patent: 6023778 (2000-02-01), Li
patent: 6055658 (2000-04-01), Jaber et al.
patent: 6115827 (2000-09-01), Nadeau-Dostie et al.
patent: 6148425 (2000-11-01), Bhawmik et al.
Copy co-pending Application w/Drawings; SC11001TH, U.S. Appl. No. 09/513,867, filed Feb. 28, 2000; entitled “Method and Apparatus For Testing An Integrated Circuit”.
Frederick Frank
Johnston Thomas K.
Chiu Joanna G.
De'cady Albert
Freescale Semiconductors, Inc.
King Robert L.
Tabone, Jr. John J.
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