LandOfFree - US Patents - Listing for Error detection/correction and fault detection/recovery,Pulse or data error handling,Digital logic testing

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Reduced signaling interface method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reduced signaling interface method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reduced-pin integrated circuit I/O test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reduced-pin-count-testing architectures for applying test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Redundancy programming for a memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Register device and methods for using such

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Register file initialization to prevent unknown outputs...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Register selection circuitry receiving select signals from...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reinstate apparatus and method to recreate data background...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Relay device and corresponding method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reliable wafer-scale integrated computing systems

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Patent

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Remote BIST high speed test and redundancy calculation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Remote BIST high speed test and redundancy calculation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Remote integrated circuit testing method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Remote test module for automatic test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Remotely monitoring execution of a program

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Patent

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Removable and replaceable tap domain selection circuitry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Removable and replaceable TAP domain selection circuitry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Remove signal from TAP selection circuitry to multiplexer...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Remove signal from TAP selection circuitry to multiplexer...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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