Reduced signaling interface method and apparatus

Details Reduced signaling interface method and apparatus Reduced signaling interface method and apparatus

2011-06-14

2011-06-14

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

07962818

ABSTRACT:
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS.41-49, provides for selectively using either the 5 signal interface of FIG.41or the 3 signal interface of FIG.8.

REFERENCES:
patent: 6631504 (2003-10-01), Dervisoglu et al.
patent: 7613970 (2009-11-01), Whetsel
Bhattacharya, D.; , “Hierarchical test access architecture for embedded cores in an integrated circuit,” VLSI Test Symposium, 1998. Proceedings. 16th IEEE , vol., No., pp. 8-14, Apr. 26-30, 1998 doi: 10.1109/VTEST.1998.670842 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=670842&isnumber=14777.
Nahvi, M.; Ivanov, A.; , “Indirect test architecture for SoC testing,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol. 23, No. 7, pp. 1128-1142, Jul. 2004 doi: 10.1109/TCAD.2004.829796 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1308406&isnumber=29034.

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