Redundancy programming for a memory device

Details Redundancy programming for a memory device Redundancy programming for a memory device

2006-12-19

2009-06-16

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S710000, C714S734000

Reexamination Certificate

active

07549098

ABSTRACT:
A method for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.

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