Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-10-23
2001-08-14
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S527000
Reexamination Certificate
active
06275962
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to automatic test equipment for testing integrated circuits, and more particularly a remote test module for use in an automatic test apparatus to interface with specialized pins of a device-under-test.
BACKGROUND OF THE INVENTION
The semiconductor device industry continually strives to manufacture smaller and faster integrated circuits in an effort to satisfy the insatiable demand for electronic products. In order to timely meet this demand with reliable IC's, device manufacturers are forced to verify the integrity and operability of each device. Consequently, a critical process involved in the successful manufacture of IC's relates to functional and structural test of each IC device.
To carry out the functional and structural tests of individual IC's, those skilled in the art often employ automatic test equipment. Commonly referred to as “testers”, the equipment applies precisely timed signal patterns or vectors to the input pins of a device-under-test (DUT), while capturing output signals from the output pins of the DUT. The output signals are compared to expected parameters resident in a memory to determine whether the IC has any functional or structural faults.
Conventional testers typically include a computer-driven test controller that issues commands to a tester interface or test head. The test head includes pin electronics that generate and send test patterns or vectors along a plurality of signal channels coupled to the individual input and output pins of the DUT. To physically interface with the DUT, the tester interface includes an array of contacts or pogos that couple to mating contacts of a device-interface-board (DIB). The DUT mounts to a socket installed on the DIB.
While conventional testers work well for their intended purposes, advances in IC technology tend to lead advances in tester technology. For example, a trend in VLSI microprocessors involves implementing a high-speed 30 channel Rambus interface. Due to the high-frequency patterns required to drive signals through such an interface (approx. 1 Gigahertz), conventional testers have difficulty achieving the required timing accuracy of about 50 picoseconds. In this particular example, some of the inaccuracy results from impedance mismatches that occur when the pulse widths driven to or received from the DUT are less than the round-trip-delay (RTD) from the tester drive/compare node to the DUT pin.
Similar problems result from other specialized DUT pins such as unexpectedly high or low voltage levels, and relatively fast or slow pattern rise-times. Thus, the key problem involves the inability for conventional testers to adapt to special DUT pins in a cost-effective and practical manner.
One conventional, and costly, technique for adapting a conventional tester to a modified DUT involves customizing the device-interface-board that mounts the DUT. Commonly referred to as a “loadboard”, the custom DIB employs special circuitry permanently fixed to the DIB and controlled by the user to interface the special DUT pins to the tester. Although this solution permits testing of the DUT by the conventional tester, limitations on the area of the DIB limits the amount of custom circuitry that can be installed. Consequently, only a few specialized DUT pins may be supported with the loadboard technique. Additionally, the calibration between the custom circuitry on the loadboard and the tester becomes problematic since the DIB is typically fabricated and controlled by the user.
Therefore, the need exists for a tester having the capability of selectively testing specialized pins of a DUT without the burden of customizing respective DIBs. Moreover, the need exists for a remote test module that adapts a tester to a multitude of DUTs having varying specialized test requirements, without the need for separate testers. The remote test module of the present invention satisfies these needs.
SUMMARY OF THE INVENTION
The remote test module of the present invention provides a convenient interface to extend the usefulness of a tester beyond its originally designed purposes, and to adapt the tester to test DUT's having specialized pins in addition to normally expected pins. The invention enables users to avoid the undesirable costs associated with customizing DIBs, or even purchasing additional specialized testers. Moreover, because the invention is implemented with the tester, calibration and debugging time is significantly reduced.
To realize the foregoing advantages, the invention, in one form, comprises a remote test module for selectively interfacing a plurality of test channels between a tester interface and a plurality of specialized pins connected to a device-under-test. The tester interface is coupled to a test controller for generating predetermined test signals. The remote test module includes a signal conditioner responsive to the test controller for modifying the predetermined test signals into module test signals and applying the module test signals to the specialized pins of the device-under-test and a connection apparatus. The connection apparatus has a plurality of conductive paths for coupling the signal conditioner between the tester interface and the specialized pins.
In another form, the invention comprises an automatic test apparatus for coupling to a device-interface-board and applying and receiving test signals to and from a device-under-test. The device-under-test is mounted to the device interface board and includes specialized test pins. The automatic test apparatus includes a test controller having a main memory configured to store a plurality of master test signals and a tester interface. The tester interface is connected to the test controller for routing a majority of the master test signals to the device-interface-board. A remote test module interfaces the tester interface to the specialized test pins and includes a signal conditioner responsive to the test controller for applying the plurality of module test signals to the device-interface-board and a connection apparatus. The connection apparatus has a plurality of conductive paths for coupling the specialized channels to the signal conditioner and connecting to the device-interface-board.
In yet another form, the invention comprises a method of adapting an automatic test apparatus to a device interface board. The device interface board mounts a device-under-test. The device-under-test includes specialized pins for receiving specialized test signals. The method includes the steps of first selecting a remote test module having a signal conditioner for receiving test signals from the test controller and modifying the signals into the specialized signals; and interposing the remote test module between the tester interface and the device-interface-board to apply the specialized signals to the specialized pins.
A further form of the invention comprises a method of minimizing timing errors on high frequency signals controlled by a test controller. The signals comprise pulses of a predetermined minimum pulse width and applied to a plurality of specialized pins on a device-under-test. The device-under-test is disposed on a device-interface-board. The method includes the steps of first selecting a remote test module having a signal conditioner for multiplying the frequency of the test signals generated by the test controller; positioning the remote test module proximate the device-under-test; and interfacing the specialized device-under-test pins with the remote test module channels to establish round-trip-delay times less than the predetermined pulse widths.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 4517512 (1985-05-01), Petrich et al.
patent: 4591795 (1986-05-01), McCorkle
patent: 4730318 (1988-03-01), Bogholtz, Jr. et al.
patent: 5111459 (1992-05-01), DeVigne
patent: 5247246 (1993-09-01), Loan et al.
patent: 5293079 (1994-03-01), Knoch
Crapuchettes Charles
Fuller Jonathan
Nelson Stuart
De'cady Albert
Kreisman Lance
Teradyne, Inc.
Ton David
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