Reduced-pin-count-testing architectures for applying test...

Details Reduced-pin-count-testing architectures for applying test... Reduced-pin-count-testing architectures for applying test...

2005-12-16

2009-02-03

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000, C714S727000, C714S025000, C714S030000, C714S718000, C714S724000, C714S732000, C714S738000, C714S739000, C714S741000

Reexamination Certificate

active

07487419

ABSTRACT:
Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.

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