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Selected: P

Provision of debug via a separate ring bus in a data...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Pseudo bus agent to support functional testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pseudo random optimized built-in self-test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pseudo-random wait-state and pseudo-random latency components

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pseudo-scan testing using hardware-accessible IC structures

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Pulse generation circuit and semiconductor tester that uses...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pulsed flop with scan circuitry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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