Pulse generation circuit and semiconductor tester that uses...

Details Pulse generation circuit and semiconductor tester that uses... Pulse generation circuit and semiconductor tester that uses...

2006-08-01

2006-08-01

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S719000

Reexamination Certificate

active

07085982

ABSTRACT:
A pulse generation circuit including a pulse formation circuit for generating normal and dummy pulses according to second delay value data, a data calculation circuit for calculating first delay value data at a timing at which the pulses are generated from the pulse formation circuit according to pattern data having information for determining whether to generate pulses from the pulse formation circuit, a dummy pulse control circuit for controlling generation of a dummy pulse in a no-pulse-generation cycle from the pulse formation circuit according to the second delay value data obtained by detecting the no-pulse-generation cycle from the first delay value data, and a logical gate circuit for eliminating the dummy pulses generated from the pulse formation circuit.

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patent: 6392641 (2002-05-01), Nishimura et al.
patent: 6684355 (2004-01-01), Kawamata
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patent: 2001-124835 (2001-05-01), None

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