Pseudo-random wait-state and pseudo-random latency components

Details Pseudo-random wait-state and pseudo-random latency components Pseudo-random wait-state and pseudo-random latency components

2004-04-20

2008-08-05

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S749000

Reexamination Certificate

active

07409608

ABSTRACT:
Methods and apparatus are provided for testing logic, particularly arbitration logic on a programmable chip. Secondary components on a programmable chip are configured with delay mechanisms operable to pseudo-randomly delay responses to requests received using arbitration logic. Requests are typically generated by primary components. The delay mechanisms can be used to test the ability of a programmable chip system to handle a variety of secondary component wait-state and latency characteristics. The delay mechanism can also be used to improve system performance.

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U.S. Appl. No. 10/775,966, filed Feb. 9, 2004, by J. Orion Pritchard and Todd Wayne forMethods And Apparatus For Variable Latency Support.

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