Pseudo-scan testing using hardware-accessible IC structures

Details Pseudo-scan testing using hardware-accessible IC structures Pseudo-scan testing using hardware-accessible IC structures

1998-03-31

2000-10-31

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714728, G01R 3128

Patent

active

061417823

ABSTRACT:
The present invention, generally speaking, provides an integrated circuit testing technique in which hardware accessibility of selected components is exploited in order to avoid scan insertion overhead but achieve as good or better fault coverage than if scan insertion had been used. The term "pseudo-scan" is used to refer to the use of read and write instructions to achieve the equivalent effect as scan insertion without the addition of scan flops. Existing ATPG tools may be used without modification by performing scan insertion on a "dummy" circuit and performing ATPG on the scan-augmented dummy circuit. The resulting ATPG vectors are then modified to perform pseudo scan of selected components of the original circuit.

REFERENCES:
patent: 5696771 (1997-12-01), Beausang et al.
patent: 5703789 (1997-12-01), Beausang et al.
patent: 5903466 (1999-05-01), Beausang et al.

Affiliated with

Also associated with

Rating

Pseudo-scan testing using hardware-accessible IC structures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pseudo-scan testing using hardware-accessible IC structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pseudo-scan testing using hardware-accessible IC structures will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2065688