Pulsed flop with scan circuitry

Details Pulsed flop with scan circuitry Pulsed flop with scan circuitry

2005-12-15

2008-05-13

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C714S030000, C714S733000, C714S729000, C716S030000, C327S144000, C326S038000, C326S048000, C326S059000, C326S046000

Reexamination Certificate

active

07373569

ABSTRACT:
In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected to a storage node in the storage circuit. The storage circuit also comprises a scan latch having an input connected to a scan data input to the storage circuit and further coupled to receive a scan enable input. The scan latch is configured to store the scan data input responsive to an assertion of the scan enable input, and also comprises a second passgate connected to the storage node and having an input coupled to receive the stored scan data. Each of the first passgate and the second passgate are coupled to receive respective pairs of control signals to control opening and closing of the passgates, wherein the scan enable signal controls which of the respective pairs of control signals are pulsed. In this manner, only one of the first passgate and the second passgate is opened in a given clock cycle of a clock signal from which the pulses are generated.

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