Pseudo random optimized built-in self-test

Details Pseudo random optimized built-in self-test Pseudo random optimized built-in self-test

2005-11-22

2005-11-22

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000, C714S739000

Reexamination Certificate

active

06968489

ABSTRACT:
Flat pseudo random test patterns are provided in combination with weighted pseudo random test patterns so that the weight applied to every latch in a LSSD shift register (SR) chain can be changed on every cycle. This enables integration of on-chip weighted pattern generation with either internal or external weight set selection. WRP patterns are generated by a tester either externally or internally to a device under test (DUT) and loaded via the shift register inputs (SRIs or WPIs) into the chip's shift register latches (SRLs). A test (or LSSD tester loop sequence) includes loading the SRLs in the SR chains with a WRP, pulsing the appropriate clocks, and unloading the responses captured in the SRLs into the multiple input signature register (MISR). Each test can then be applied multiple times for each weight set, with the weight-set assigning a weight factor or probability to each SRL.

REFERENCES:
patent: 4687988 (1987-08-01), Eichelberger et al.
patent: 5612963 (1997-03-01), Koenemann et al.

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