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Method and apparatus for testing pipelined dynamic logic

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for testing semiconductor devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for the real time manipulation of a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for the testing of input/output drivers...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for transferring hidden signals in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for transforming pseudorandom binary...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for transforming system simulation...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for unifying self-test with scan-test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for unifying self-test with scan-test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for utilizing mux scan flip-flops to test s

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method and apparatus for vector processing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for virtualizing system operation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method and apparatus of boundary scan testing for AC-coupled...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus of increasing the vector rate of a digital

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method and apparatus of pre-loading a seed for a test code...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus that allows the logic state of a logic...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus that tracks processor resources in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus to disable compaction of test responses...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus to facilitate self-testing of a system...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus to facilitate self-testing of a system...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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