Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-01-16
2004-09-07
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C702S072000, C702S117000, C324S765010, C365S193000
Reexamination Certificate
active
06789224
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device testing method and apparatus suitable for use in testing semiconductor devices that have built-in fast write and read type memories.
Before entering into an explanation of the prior art to which the present invention pertains, a description will be given, with reference to
FIG. 1
, of the general outlines of a semiconductor IC tester.
The IC tester, identified generally by TES, comprises a main controller
13
, a pattern generator
14
, a timing generator
15
, a waveform formatter
16
, a logic comparator
12
, a driver
17
, a signal readout circuit
11
, a failure analysis memory
18
, a logical amplitude reference voltage source
19
, a comparison reference voltage source
21
and a device power source
22
.
The main controller
13
is usually formed by a computer system and operates under the control of a test program prepared by a user, mainly controlling the pattern generator
14
and the timing generator
15
. The pattern generator
14
generates test pattern data, which is converted by the waveform formatter
16
to a test pattern signal of the same waveform as the actual one. The test pattern signal is provided to the driver
17
from which it is output as a waveform of an amplitude value set in the logical amplitude reference voltage source
19
and is applied to a memory under test DUT for storage therein.
A response signal read out of a memory cell of the semiconductor device under test DUT is provided to the signal readout circuit
11
, wherein its logical value is read out, that is, sampled by a strobe pulse. The logic comparator
12
compares the thus read-out logical value with an expected value fed from the pattern generator
14
. If a mismatch is found between the logic value and the expectation, it is decided that a memory cell of the address from which the response signal was read out is failing, and upon each occurrence of such a failure, the faulty address is stored in the failure analysis memory
18
for use in deciding, after completion of the test, whether the failed cell is repairable.
FIG. 1
is a diagrammatic showing of the tester configuration for one pin alone, but in practice the depicted configuration is provided for each pin of the memory DUT; that is, for each pin the test pattern is input to the memory DUT and the response signal is read out therefrom.
Among semiconductor memories is a memory (hereinafter referred to also as a semiconductor device)of the type that performs the writing and reading of data thereto and therefrom in synchronization with a clock.
FIG. 2
shows how this kind of memory is read out.
FIG. 2A
depicts pieces of data DA, DB, DC, . . . that are output from (a pin of) memory, respective test cycles TD
1
, TD
2
, TD
3
, . . . being divided off by broken lines.
FIG. 2B
shows a clock DQS that is output from the memory. As shown, the pieces of data DA, DB, DC, . . . are output from the memory in synchronization with the clock DQS. When the semiconductor IC is in actual use, the clock is used as a sync signal (data strobe) to pass the pieces of data DA, DB, DC, . . . to other circuits.
The testing the semiconductor device of this kind includes an item of measuring time difference or intervals (phase differences) dI
1
, dI
2
, dI
3
, . . . between the rise and fall timing of the clock (hereinafter referred to as a reference clock) DQS and the points of change of the data. The smaller the time differences, the faster the response and consequently the higher the level of performance characteristic. In other words, the grade of the memory under test depends on the above-mentioned time differences.
While the semiconductor device (memory) is in actual use, a clock from a clock source is applied to a circuit in the semiconductor device, from which data is output in synchronization with the clock. Accordingly, in the testing of the semiconductor device by the tester, too, a clock is fed from the tester to the semiconductor device under test and is passed through its internal circuit, thereafter being output therefrom, together with data, as the reference clock DQS for providing the output data to the tester. The tester measures the rise and fall timing of the reference clock DQS and the time intervals dI
1
, dI
2
, dI
3
, . . . between the measured timing of the rise and fall of the reference clock DQS and the points of change of the pieces of data DA, DB, DC, . . .
Since the reference clock DQS is output from the semiconductor device under test after passing through its inside as mentioned above, the rise and fall timing of the reference clock DQS is greatly affected by internal circuit operations of the semiconductor device under test and environmental conditions such as ambient temperature. For example, as depicted in
FIG. 3
in which there are shown reference clock pulses DQSA, DQSB and DQSC that are output from individual semiconductor devices under test A, B and C, the reference clock pulses DQSA, DQSB and DQSC are phased apart. This phase difference is caused not only by device-to-device variation but also by the difference in the memory address accessed in the respective semiconductor device and by jitter J of the rise and fall timing of each reference clock that is caused by an increase in the device temperature due to an extended period of operation as indicated by the broken lines.
With the point of measurement set at timing with too wide a margin of safety against such variations or fluctuations in performance characteristics of the devices under test, there is fear of a device of normal operation being decided as defective; the possibility of such a wrong decision gets stronger particularly with an increase in the operating frequency of the device.
Accordingly, it is necessary to accurately measure the time intervals dI
1
, dI
2
, dI
3
, . . . between the rise and fall timing of the reference clock DQS and the points of change of the pieces of data DA, DB, DC, . . . This requires accurate measurement of the rise and fall timing of the reference clock DQS.
To this end, it is customary in the prior art to measure the rise and fall timing of the reference clock DQS while gradually shifting the timing for the application of the strobe pulse to the signal readout circuit of the tester, the measurement results being used to measure the time intervals dI
1
, dI
2
, dI
3
, . . . .
FIG. 4
is a block diagram depicting a conventional arrangement for measuring the rise and fall timing of the reference clock DQS. A level comparator
10
comprises a pair of voltage comparators CP
1
and CP
2
, by which it is decided whether the logical value of the reference clock DQS output from the semiconductor device DUT satisfies normal voltage conditions. The voltage comparator CP
1
decides whether the voltage value of the logical “H” value of the reference clock DQS is above a normal voltage value VOH. The voltage comparator CP
2
decides whether the voltage value of the logical “L” value of the reference clock DQS is below a normal voltage value VOL.
These decision results are provided to the signal readout circuit
11
, which measures the rise and fall timing of the reference clock DQS. Upon each application thereto of the strobe pulse STB, the signal readout circuit
11
reads out the logical value input at that time.
FIG. 5A
shows the reference clock DQS that is provided for each test cycle TD.
FIG. 5B
shows strobe pulses STB that are applied to the signal readout circuit
11
over a sequence of test cycles TD. The strobe pulses STB are phased &tgr;T apart with respect to the reference clock DQS as depicted in FIG.
5
B. That is, for each test cycle the strobe pulse STB is applied to the signal readout circuit
11
to read out (sample) the outputs from the voltage comparators CP
1
and CP
2
. The output-side arrangement of the voltage comparator CP
2
, though not shown in
FIG. 4
, is identical with the depicted arrangement of the voltage comparator CP
1
.
The logic comparator
12
compares the logical value output from the signal readout circuit
Advantest Corporation
De'cady Albert
Dooley Mathew C.
Gallagher & Lathrop
Lathrop, Esq. David N.
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