Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-12-07
2001-09-25
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C345S418000
Reexamination Certificate
active
06295622
ABSTRACT:
BACKGROUND OF THE INVENTION
1 Field of the Invention
The present invention relates to the field of electronics, and more particularly to the field of testing of electronic devices.
2. Description of the Related Art
Electronic devices have been fabricated from CMOS technology for many years. CMOS technology is made possible by the fabrication of p-channel field effect transistors (PFETS) and n-channel field effect transistors (NFETS) on a common substrate. CMOS devices have an enormous advantage over devices fabricated according to other technologies, in that CMOS devices generally consume very low DC power and very low AC power at low frequencies.
Many logic families fabricated of CMOS technologies have been described in the literature. Static CMOS logic, domino logic, and dynamic precharge logic have been described and have become well known in the field of electronics. However, a new family, known as the N-nary logic family, has also been developed. N-nary devices are disclosed in copending applications, U.S. Pat. application. Ser. No. 09/019244, filed Feb. 5, 1998, now U.S. Pat. No. 6,069,497, entitled “Method and Apparatus for a N-Nary logic circuit using 1ofN encoding,” and U.S. Pat. application. Ser. No. 09/179,330, filed Oct. 27 1998, entitled “Method and Apparatus for Logic Synchronization,” now U.S. Pat. No. 6,118,304, both of which are incorporated by reference into this application.
N-nary signals are quite different from binary signals. Binary signals typically implement each bit on a distinct wire (parallel bus), or each bit one-at-a-time over a common wire (serial bus). The N-nary signals, in contrast, encode at least one bit, and in many cases more than one bit, over a group of wires. The group of wires collectively implements the N-nary signal, which can contain one bit or more than one bit.
Of the wires in an N-nary signal, however, at most one can have a high voltage. For example, in a “1-of-4” N-nary signal, four wires are used to implement two bits of information, having collectively four states. In a first state, the first wire is “hot,” meaning having a high voltage. In a second state, the second wire is “hot;” in a third state, the third wire is “hot;” and in a fourth state, the fourth wire is “hot.” In contrast, to achieve four distinct states in binary logic, two wires are used.
The nature of the N-nary logic family has presented certain challenges for testing. When a tester applies a test vector to an N-nary logic device, the test vector should be legal and realizable within the “rules” of N-nary logic, since testing how a device responds to stimuli that the device will never actually experience is inefficient and possibly useless. Moreover, applying test vectors that are not legal can have unpredictable results and might even damage the circuit under test, since the circuit likely was not designed to handle such signals. Unfortunately, testers have generally been designed to apply binary signals to circuits under test, and some binary signals are not legal N-nary signals. In N-nary logic, a signal is legal if the signal includes at least two wires, and no more than one of the wires may have a high logic level at any time.
Generally, N-nary numbers are the most efficient stimuli for exposing faults in N-nary circuits. N-nary numbers are formed of the collection of at least one N-nary signal. Each N-nary signal represents a “digit” or portion of the number. For example, the number “fifteen” implemented in 1-of-4 N-nary logic would require two N-nary signals, one of which represents the higher-order 1-of4 value (the two most significant bits worth of information) and the other of which represents the lower-order 1-of4 value (the least two significant bits of information).
One way to iterate through all possible test vectors is to count the numbers from 1 to the highest number that may be implemented. For example, in binary, to iterate through all possible test vectors, it is possible to count the binary numbers. Counting the binary numbers from 1 to 2
n
−1 in binary provides a value for each of n bits, and associating each of the bits with a wire of the test vector provides a logic level for the circuit under test. Similarly, in N-nary, to iterate through all possible test vectors, it is possible to count the N-nary numbers. Counting the N-nary numbers from zero to N, however, provides a value for each of N wires of the test vector, and provides a logic level for the circuit under test.
In binary, iterating through all possible binary numbers from 1 to 2
n
−1 may be accomplished through the use of an n-bit counter. An n-bit counter may be implemented by n one-bit flip-flops in sequence. However, such an n-bit counter merely iterates through all of the binary numbers from 1 to 2
n
−1 in consecutive order. To iterate through all of the binary numbers from 1 to 2
n
−1 in a non-consecutive order, other structures have been developed. One such structure is the linear finite state machine, or LFSM. LFSMs that have n cells generally have been used to produce all of the binary numbers from 1 to 2
n
−1 in a non-consecutive order. The binary numbers from 1 to 2
n
31 1 produced by well-known LFSMs have generally been satisfactory for testing binary logic devices. For example, a circuit under test is partitioned into various test points, and each wire in a test point is associated with a distinct bit of a test vector. This is the built-in self-test (BIST) approach described in the co-pending application “Method and Apparatus For Built-in Self-test of Logic Circuitry,” U.S. Pat. application. Ser. No. 09/191,183, filed Nov. 13 1998, which is incorporated by reference into this application. This approach is not necessarily true for other BIST implementations, however. Conventional BIST just hooks each cell to a primary input without partitioning per se. Other approaches used by well-known LFSMs include the LFSM producing test vectors that fully test the logic under test by achieving every possible input state (this type of testing is generally called “exhaustive testing”). More typically, however, the LFSM only generates a subset of the 2
n
−1 numbers because it takes too long to generate all of the possible numbers. Indeed, there is a whole sub-field of testing concerned with how to guarantee test coverage without testing exhaustively that is not within the scope of this disclosure.
SUMMARY
The present invention comprises a number transformer that includes an encoder that converts binary numbers to N-nary numbers. Within an N-nary number, exactly one of the bits has a value of one and all of the remaining bits have a value of zero. According to some aspects, several N-nary numbers are generated in response to a binary number. A set of encoding instance selectors defines a partitioning of the bits of the binary number and a range of bits within each partition. The encoder then converts each subset of bits of the binary number to a corresponding N-nary number, such that exactly one of the bits of each N-nary number has a value of one and all of the remaining bits of the N-nary number have a value of zero, and such that the one of the bits of each N-nary number having a value of one is within the range of bits defined by the corresponding encoding instance selector. The set of encoding instance selectors may define a test point within a circuit under test, and may be produced by an on-chip ROM.
Additionally, the present invention comprises a number transformer that includes at least one updatable parameter, for example a ring counter, that produces an N-nary number. The N-nary number has several bits, exactly one of which has a value of one and the remaining of which have a value of zero. The number transformer also includes a masker, configured to perform a bitwise boolean AND upon the first updatable parameter and a binary number. The binary number is obtained from a linear finite state machine operating as a pseudorandom pattern generator. When several ring counters are included, multiplexers are added to select one of the ring co
Amanze Emeka J.
Booth Matthew J.
Booth & Wright, L.L.P.
De'cady Albert
Intrinsity, Inc.
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