Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-03-23
2004-09-14
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C380S268000, C380S046000
Reexamination Certificate
active
06792566
ABSTRACT:
This application incorporates by reference Taiwanese application Ser. No. 89105531, filed on Mar. 24, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method and an apparatus of loading a seed for a test code of a physical layer device (PHY), and more particularly to a method and an apparatus of loading a pre-load seed to a scrambler and a descrambler of a PHY so as to correctly load a test code to the PHY for testing the quality of the PHY.
2. Description of the Related Art
Computer networks for searching for information, sending email, etc have become indispensable in today's industry, academia, and daily lives. Computer networks include wide area networks (WAN), such as Internet, and local area network (LAN), such as an Ethernet LAN. Usually, a personal computer connects to another computer through a computer network, such as the Internet, either by a modem or a network interface card (NIC).
FIG. 1
is a block diagram illustrating the connecting relationships between PHYs of a transmitting end and a receiving end. Referring to
FIG. 1
, a PHY
102
receives signals from a media independent interface (MII)
100
. After the signals are processed, they are transmitted through a transformer
104
which filters out the DC components of the signals and sends the resulting signals to a medium
106
, such as a cable. Then, a PHY
110
at the receiving end receives the signals from transformer
108
and transmits the signals to a MII
112
for further processing.
FIG. 2A
is a block diagram illustrating the internal structure of the PHY
102
of the transmitting end shown in
FIG. 1
, wherein a scrambler
206
uses a seed to scramble data.
FIG. 2B
is a block diagram illustrating the internal structure of the PHY
110
of the receiving end shown in
FIG. 1
, wherein a descrambler
218
uses a seed to descramble the scrambled data. Referring to
FIG. 2A
, 4-bit (4B) symbols, which are transmitted from the MII
100
to the PHY
102
, are converted to 5-bit (5B) symbols by a 4B/5B converter
202
. Then, a parallel/serial (P/S) converter
204
receives the resulting 5B symbols and converts it from parallel to serial symbols. Next, the scrambler
206
uses a seed to scramble serial symbols to a non-return-to-zero (NRZ) signal, wherein NRZ is a coding scheme. Then, an NRZ/NRZI converter
208
converts the NRZ signal to a non-return-to-zero-inverted (NRZI) signal, wherein NRZI is also a coding scheme. Afterwards, an NRZI/MLT3 converter
210
converts the NRZI signal to a multiple-level-transmit 3 (MLT3) signal, wherein MLT3 is a coding scheme for transmission in 100 MHz Ethernet.
Referring to
FIG. 2B
, the MLT3 signal outputted by the NRZI/MLT3 converter
210
shown in
FIG. 2A
is transmitted through a transmission line to the PHY
110
of the receiving end. The MLT3/NRZI converter
214
receives the MLT3 signal and converts it to an NRZI signal. The NRZI/NRZ converter
216
receives the NRZI signal and converts it to an NRZ signal. Then, a descrambler
218
uses the seed to descramble the NRZ signal to the original serial symbols before being scrambled. An S/P converter
220
converts the serial symbols to parallel symbols and transmits the results to a 5B/4B converter. Afterwards, 5B symbols of the serial symbols are converted to 4B symbols. Then, the 4B symbols are transmitted to the MII
112
.
During the process of the transmission, if 5B symbol matches with the seed used by the scrambler
206
, the output of the scrambler
206
is in the low level. Then, the level of the NRZI signal is kept constant so as to fix the MLT3 signal in one of the three levels, i.e. the low level, high-resistance level, or the high level. However, when the level of the MLT3 signal is kept in low or high, the DC component of the MLT3 signal either increases or decreases, which results in the so-called base line wander phenomenon.
The base line wander phenomenon is caused basically by transformers in the transmitting end and the receiving end. The transformers can filter out the DC component of a signal while allowing the AC component to be transmitted. The DC component of the MLT3 signal influences the base line wander phenomenon. When the base line wander phenomenon exceeds the tolerance of PHY
212
, the received signals are then erroneous.
As a result, the degree of the base line wander phenomenon can be used as a basis for testing the quality of PHY. For example, the test pattern for baseline wander measurements defined in ISO9314-1 standard provides a 9000-symbol fiber distributed data interface (FDDI) frame as a worst case pattern to test the quality of PHY.
A PHY tester, in a testing house, can generate a “test vector” containing the exact period for transmitting the first 5B symbol and an idle period with precise and complicated computation. Therefore, when to generate the correct seed can be predicted. However, too much time is required for the PHY tester to generate the test vector and the cycle-based operation is inefficient. Also, the cost is high. Specifically, these disadvantage the chip designer a lot. Moreover, it is difficult to test the test vector on a bench board directly since an expensive pattern for baseline wander measurements generator is required to control the precise timing and generate the pattern for baseline wander measurements.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method and an apparatus of loading a pre-load seed for a test code of a physical layer device (PHY). According to the invention, a frame starting-bits detector is used to determine the correct time to pre-load the seed. In addition, a feedback controller is used to keep the NRZI signal in the high level, which allows the correct transmitting and receiving of the test code possible. In this way, the test code can correspond to a pattern for baseline wander measurements, such as one defined in ISO9314-1. Thus, the quality of a PHY can be tested and both cost and time can be reduced.
The invention achieves the above-identified objects by providing a method of loading a pre-load seed for a test code of a physical layer device. The physical layer device includes a scrambler and a Non-Return-to-Zero/Non-Return-to-Zero-Inverted (NRZ/NRZI) converter, and the NRZ/NRZI converter is connected to the scrambler, receives an NRZ signal outputted by the scrambler, and outputs an NRZI signal. The method includes the following steps. (a) Determine whether a plurality of starting bits of a frame are present. (b) Repeat from step (a) if the starting bits are not present. (c) Load the pre-load seed to the scrambler. (d) Set the NRZI signal in a high level when the NRZI signal is not in the high level, and keep the NRZI signal in the high level when the NRZI signal is in the high level. (e) Transmit the test code.
The invention achieves the above-identified objects by providing a method of loading a pre-load seed of a test code in a physical layer device having a descrambler. The method includes the steps of: (a) determining whether a plurality of starting bits of a frame are present; and (b) loading the pre-load seed to the descrambler to retrieve the test code.
The invention achieves the above-identified objects by providing an apparatus of loading a pre-load seed of a test code of a physical layer device (PHY). The PHY includes a scrambler and a Non-Return-to-Zero/Non-Return-to-Zero-Inverted (NRZ/NRZI) converter. The NRZ/NRZI converter is used for receiving an NRZ signal outputted by the scrambler and outputting an NRZI signal. The apparatus includes a seed-preload controller. The seed-preload controller receives a first signal inputted to the scrambler and the NRZI signal, and is used for detecting a number of starting bits of a frame of the test code, outputting a loading seed signal to the scrambler to load the pre-load seed, and keeping the NRZI signal in a high level when the NRZI is in the high level. In addition, the seed-preload controller sets the NRZI signal in the high level by changing a bit of a first symbol of the test code when th
Chang Chin-Chi
Chen Chung-Heng
Rabin & Berdo P.C.
Tu Christine T.
Via Technologies Inc.
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