Method and apparatus of increasing the vector rate of a digital

Details Method and apparatus of increasing the vector rate of a digital Method and apparatus of increasing the vector rate of a digital

1997-01-29

2000-06-13

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128, G06F 1100

Patent

active

060761792

ABSTRACT:
The present invention provides a method and apparatus for increasing the vector rate of an integrated circuit test system and simplifying the wiring of the tester to the device under test. The tester incorporates circuitry that allows the CPU to remap assignments of tester channels in the CPU address space during testing.

REFERENCES:
patent: 4379259 (1983-04-01), Varadi et al.
patent: 4929889 (1990-05-01), Seiler et al.
patent: 5432797 (1995-07-01), Takano
patent: 5497079 (1996-03-01), Yamada et al.
patent: 5608337 (1997-03-01), Hendricks et al.
patent: 5682472 (1997-10-01), Brehm et al.
patent: 5723375 (1998-03-01), Ma et al.

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