Device and method for verifying independent reads and writes in
Device for margin testing a semiconductor memory by applying...
Device for margin testing a semiconductor memory by applying...
Device for the structural testing of an integrated circuit
Device to check the end of a test
Device with integrated SRAM memory and method of testing...
Diagnostic data port for a LSI or VLSI integrated circuit
Diagnostic data port for a LSI or VLSI integrated circuit
Differential cell-type EPROM incorporating stress test circuit
Digital testing of analog memory devices
Direct bit line-bit line defect detection test mode for SRAM
Direct memory access interface in integrated circuits
DRAM compressed data test mode with expected data
DRAM having test circuit capable of performing function test of
DRAM signal margin test method
Dram with reduced-test-time mode
DRAM with reduced-test-time-mode
Driver circuit for a voltage-pulling device
Dual in-line memory module, memory test system, and method...
Duty-cycle-efficient SRAM cell test