DRAM compressed data test mode with expected data

Details DRAM compressed data test mode with expected data DRAM compressed data test mode with expected data

1991-01-31

1993-07-27

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

371 212, 371 251, G11C 700, G11C 2900

Patent

active

052316050

ABSTRACT:
A unique method of testing an integrated circuit DRAM for incorrect stored data is disclosed. A JEDEC test mode entry is initiated by normal means, i.e., Write Enable (WE*) and Column Address Select (CAS*) before Row Address Select (RAS*) with specific address data to select a specific test. Data bits are then loaded in the DRAM cells and column data bits compared. The subarray bits are also compared with bits in an expected data register which has been loaded at the beginning of the read cycle. If column bits match and subarray bits match the expected data register, ones are indicated on the data (out) bus; otherwise, a zero appears in case of a data error.

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