Differential cell-type EPROM incorporating stress test circuit

Details Differential cell-type EPROM incorporating stress test circuit Differential cell-type EPROM incorporating stress test circuit

1991-03-22

1993-09-07

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Testing

365207, G11C 700

Patent

active

052435695

ABSTRACT:
A differential cell-type non-volatile semiconductor device having first and second memory cell is disclosed. Two cell transistors of corresponding addresses in the first and second memory cell arrays are used to constitute a single memory cell. Each of writing transistors for writing data in the cell transistors is provided to the first and second memory cell arrays. Complementary data are written in the two cell transistors selected in the first and second memory cell arrays. Readout potentials from the two cell transistors are amplified by a differential amplifier, thereby reading out stored data. The memory device has a stress test control circuit for controlling, in a stress test mode, writing transistors such that they are all simultaneously turned on/off.

REFERENCES:
patent: 4970691 (1990-11-01), Atsumi et al.
"A 25ns 16K CMOS PROM Using A 4-Transistor Cell." ISSCC 1985 Digest of Technical Papers.

Affiliated with

Also associated with

Rating

Differential cell-type EPROM incorporating stress test circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Differential cell-type EPROM incorporating stress test circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Differential cell-type EPROM incorporating stress test circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-493082