DRAM having test circuit capable of performing function test of

Details DRAM having test circuit capable of performing function test of DRAM having test circuit capable of performing function test of

1996-04-03

1997-04-29

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Testing

365222, 365203, G11C 2900

Patent

active

056255977

ABSTRACT:
According to the present invention, there is provided a circuit structure capable of carrying out the function test of the refresh counter and the measurement of the counter cycle at the time of the refresh operation. The counter generates a refresh row address. The bit line sense amplifier circuit connected to a bit line pair for transmitting data of a memory cell, consists of the N-channel sense amplifier and the P-channel sense amplifier. The sense amplifier driving circuit supplies respective driving signals for the N-channel sense amplifier and the P-channel sense amplifier. The test control circuit is provided for carrying out the function test of the refresh counter and the measurement of the counter cycle at the time of the refresh operation, and controls the driving signals so as to set one of the N-channel sense amplifier and the P-channel sense amplifier in a non-active state at the time of a test mode.

REFERENCES:
patent: 4347589 (1982-08-01), Proebsting
patent: 4807196 (1989-02-01), Mizukami
patent: 5321661 (1994-06-01), Iwakiri et al.
patent: 5418754 (1995-05-01), Sakakibara
patent: 5450364 (1995-09-01), Stephens, Jr. et al.
patent: 5471430 (1995-11-01), Sawada et al.
patent: 5502677 (1996-03-01), Takahashi

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