DRAM signal margin test method

Details DRAM signal margin test method DRAM signal margin test method

1995-09-28

1997-03-11

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Testing

36518905, 36518907, 36523006, G11C 700, G11C 2900

Patent

active

056108672

ABSTRACT:
In the Preferred embodiment of the present invention, a bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level. Additionally, because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, as in prior art signal margin tests, cell signal margin is tested by varying cell signal. V.sub.S may be selected to determine both a high and a low signal margin.

REFERENCES:
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patent: 5157629 (1992-10-01), Sato et al.
patent: 5187685 (1993-02-01), Sato et al.
patent: 5265056 (1993-11-01), Butler et al.
patent: 5497458 (1996-03-01), Finch et al.
patent: 5513193 (1996-04-01), Hashimoto
K. S. Gray, et al., "Sense Amplifier Signal Margin Circuit" IBM Technical Disclosure Bulletin, vol. 22, No. 1, pp. 56-57, Jun. 1979.
D. G. Morency, et al, "Bit Line Offset Circuit" IBM Technical Disclosure Bulletin, vol. 27, No. 7B, pp. 4126-4127, Dec. 1984.
"Signal Margin Test For 4-D,4-D With Poly Load Or 6-D Random-Access Memories" IBM Technical Disclosure Bulletin, vol. 28, No. 11, pp. 4792-4793, Apr. 1986.

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