1-T memory structure capable of performing hidden refresh...
1-transistor type DRAM cell, DRAM device and DRAM comprising...
1.8 volt output buffer on flash memories
2-cell/1-bit type EPROM
2-D FIFO memory having full-width read/write capability
256 Meg dynamic random access memory
2T2C signal margin test mode using a defined charge and...
2T2C signal margin test mode using a defined charge exchange...
2T2C signal margin test mode using resistive element
3-level non-volatile semiconductor memory device and method...
4-bit prefetch-type FCRAM having improved data write control...
4N pre-fetch memory data transfer system
5-Transistor memory cell which can be reliably read and written
5-transistor memory cell with known state on power-up
6F2 DRAM array with apparatus for stress testing an...
6F2 DRAM array with apparatus for stress testing an...
A gaas register file having a plurality of latches
AC sensing for a resistive memory
AC sensing for a resistive memory
AC Transient driver for memory cells