Device for the structural testing of an integrated circuit

Details Device for the structural testing of an integrated circuit Device for the structural testing of an integrated circuit

1990-09-24

1991-10-22

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Testing

36518908, 36523006, 371 211, 371 221, 371 251, 371 212, G11C 2900

Patent

active

050601989

ABSTRACT:
Between a bit line decoder and the memory of an integrated circuit, there is interposed a gate circuit which is cascade-connected with a logic block of the integrated circuit. This arrangement makes possible the structural testing of the integrated circuit. Structural testing means to read and check the response given on the outputs of the logic blocks for a given state imposed on its inputs. This arrangement results in a reduction of the space required on the integrated circuit for testing, when compared with other solutions, which require specific connection circuits. This arrangement is particularly adapted to integrated circuits with a memory and with decoders that provide access to the memory. The arrangement will find particular application in the testing of memory cards where EPROM or EEPROM circuits are used.

REFERENCES:
patent: 4481627 (1984-11-01), Beauchesne et al.
patent: 4603405 (1986-07-01), Michael
patent: 4720818 (1988-01-01), Takeguchi
patent: 4742989 (1988-05-01), Hoffmann
patent: 4752929 (1988-06-01), Kantz et al.
patent: 4829520 (1989-05-01), Toth
Integration to VLSI Journal, vol. 2, 12/84, pp. 309-330, K. K. Saluja et al., "Testable Design of Large Random Access Memories".
Electro and Mini/Micro, 4/23-25/85, pp. 1-4, S. Grossman, "Testing Today's EEPROMs".

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