RAM memory circuit having a plurality of banks and an...
Random access memory including circuit to compress...
Random access memory with a plurality amplifier groups for readi
Random access memory with a simple test arrangement
Random access memory with rapid test pattern writing
Read complete test technique for memory arrays
Read compression in a memory
Read leveling of memory units designed to receive access...
Read only memory capable of writing data and method of writing/r
Read/write memory device with an embedded read-only pattern and
Read/write memory with improved test mode data compare
Real-time adaptive SRAM array for high SEU immunity
Reconfigurable built-in self test circuit
Recording of result information in a built-in self-test...
Reduced pin count stress test circuit for integrated memory devi
Redundancy analysis for embedded memories with built-in self tes
Redundancy test method for a semiconductor memory
Redundant memory structure using bad bit pointers
Redundant memory structure using bad bit pointers
Refresh characteristic testing circuit and method for...