Dram with reduced-test-time mode

Details Dram with reduced-test-time mode Dram with reduced-test-time mode

1988-12-01

1989-08-22

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Testing

36518901, 365226, 36518911, 371 21, G11C 700, G11C 2900

Patent

active

048602590

ABSTRACT:
In a semiconductor memory device comprising a plurality of memory cells, a test request detection circuit responds to a voltage, on an input terminal, higher than a range of voltages supplied under ordinary operation condition for producing a test signal. Responsive to the test signal, data which has been supplied to the semiconductor memory device are simultaneously written into a plurality of memory cells, and data are simultaneously read from a plurality of memory cells, and judgement is made as to whether or not the data from the memory cells coincide with the data originally supplied to the semiconductor memory device.

REFERENCES:
patent: 4055754 (1977-10-01), Chesley
patent: 4543647 (1985-09-01), Yashida
patent: 4612630 (1986-09-01), Rosier
patent: 4654849 (1987-03-01), White, Jr. et al.
patent: 4672583 (1987-06-01), Nakaizami
patent: 4686456 (1987-08-01), Furuyama et al.
M. T. Sworakowski, "Redundant Clock Magnetic Recording", vol. 12, No. 2, Jul. 1969, p. 254.
Inoue et al., "An 85ns 1Mb DRAM in a Plastic DIP", ISCC 85, pp. 238-239, Feb. 15, 1985.
Kumanoya, et al., "A 90ns 1Mb DRAM with Multi-Bit Test Mode", ISSCC 85, pp. 240-241, Feb. 15, 1985.
"RAM Internal Parallel Testing Technique", Cady et al., IBM Technical Disclosure Bulletin, vol. 27, No. 7B, (Dec. 1984) pp. 4534-4536.

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