Duty-cycle-efficient SRAM cell test

Details Duty-cycle-efficient SRAM cell test Duty-cycle-efficient SRAM cell test

2001-07-17

2002-09-10

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S194000

Reexamination Certificate

active

06449200

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the testing of semiconductor memory cells and more particularly to an improved method and structure for stressing and testing contacts within semiconductor structures.
2. Description of the Related Art
A typical semiconductor static random-access memory (SRAM) device includes word lines, a pair of bit lines, and memory cells with cell latches and pass devices connected at intersections between the word lines and the pair of bit lines. The pass devices of the memory cells are connected to the pair of bit lines through bitline contacts. During a read or write operation, these bitline contacts allow the contents of the memory cell to be successfully read from or written into the cell latch. Bitline contacts that have too much resistance (resistive bitline contacts) will not properly allow the memory cell to be read from or written into. Resistive bitline contacts may occur as a result of mechanical failures or non-conductive materials that are formed between the pass devices and the bitline, and are hard to detect since the pass devices have a large series resistance (e.g., typically in the 10 Kohm range) compared to the resistive bitline contact.
Although bitline contacts may be tested with the testing of the memory cell or bitlines, most manufacturing tests have difficulty recognizing a borderline resistive bitline contact and will generally pass the bitline contact and memory cell. When the resistive bitline contact is then used in the system under a slightly different voltage and/or temperature, the resistive bitline contact may then fail, rendering the corresponding memory cell inoperable.
The six-transistor SRAM cell shown in
FIG. 1
continues to be the workhorse in both embedded and stand-alone high-performance SRAM arrays. In
FIG. 1
, the wordline is represented by WL, the bitline true and a bitline complement are represented by BLT and BLC, respectively, the various transistors are represented by an upper case “T” followed by a distinguishing number, and the nodes of the cell are identified as “A” and “B”. The performance advantage of the six-transistor SRAM cell is attributed to the fully differential rail-to-rail cell nodes (nodes A and B in
FIG. 1
) that provide the maximum overdrive to cross-coupled N-type field effect transistors (NFET) devices T
3
and T
4
during a read cycle.
Furthermore, cell nodes are fully written shortly after the activation of the wordline as P-type field effect transistors (PFET) devices T
1
or T
2
restore a full differential on a cell node that would otherwise be partially written to approximately VDD-Vtn through wordline devices T
5
or T
6
. The strength of the wordline devices T
5
and T
6
is normally designed to be weaker than that of the latch pull-down devices T
3
and T
4
to maintain cell stability, especially during high voltage operation and burn-in. The latch pull-down devices are designed to supply enough read current (with wordline devices in series) to discharge 100 mV from a VDD-precharged bitline in 700 ps. Such device characteristics result in a very high impedance bitline discharge path.
FIG. 2
shows an equivalent schematic representation of the bitline and cell during a read cycle. Prior to the start of a read cycle, a distributed bitline capacitance (CBL) is precharged to VDD. A bitline is then discharged through the following components: bitline resistance (RB), bitline contact resistance (RC), wordline device resistance (RW) (T
5
in FIG.
1
), and finally latch pull-down device resistance (RD) (T
3
in FIG.
1
). Typical resistances for all components are also shown. The resistance of a good bitline contact (RC) normally ranges from 2&OHgr;-5&OHgr; while the combined series resistance of the wordline device and the latch pull-down device is approximately 15 K&OHgr;, as shown in FIG.
2
.
The source/drain structures are commonly used by adjacent memory cells and are isolated from each other with Shallow Trench Isolation (STI). Above the STI there is generally layer of silicon nitride that is used as an etch stop for the contacts. The contacts are drilled first through the dielectric, and then through the nitride, exposing the silicided silicon surface. The contacts are generally lined with titanium nitride then filled with tungsten.
However, if the contact and source/drain regions are not properly aligned, if the opening for the contact is not formed completely through the insulator to the source/drain region, or if the conductive material does not completely fill the contact opening, there can be substantial resistance between the source/drain regions of the transistor and the contact material. For example, the silicon nitride may not be substantially removed prior to deposition of the metal in the contact opening. In such a situation, it is difficult to locate the actual conduction path through this failing contact. Since the expected resistance of the metallic stack including the contact is on the order of a few ohms, it can be predicted that the original resistance of the defective stack was on the order of many thousands of ohms.
Thus, the relationship between the bitline contact resistance and the devices series resistance makes it extremely difficult to detect marginal, resistive and unreliable bitline contacts. Process defects can cause significant increases in the bitline contact resistance with little or no impact on the SRAM read operation.
FIG. 3A
shows the waveforms of a read cycle with bitline contacts having different RC (RC=5&OHgr; and RC=20 K&OHgr;) as well as the timing of the setting of the sense amplifier (SET) and the timing of the wordline pulse (WL).
Even when the resistance is changed a very large amount (from 5&OHgr; to 20,000&OHgr;), the signal loss at the sense-amplifier at the time of setting is only 39%. This is shown in
FIG. 3B
where the signal loss of 46 mV (118 mV−72 mV) between the different bitline contact resistances is shown at the time the sense amplifier is set (SET). Thus, as shown, any significant increase in bitline-contact resistance caused by a defect will not disturb a read cycle to the point of failure. Indeed, read cycles may only be effective in detecting and screening resistive bitline contacts with resistances greater than 40 K&OHgr;.
To the contrary, resistive bitline contacts are far more critical during a write operation because a differential write driver must overcome the cell latch nodes through wordline devices T
5
or T
6
and bitline contact resistance RC. The amount of signal excursion that must occur at the cell nodes has to be greater than 60% of the supply level to overcome the latch PFET-feedback device. At this point, the latch is then flipped and the latch NFET device finalizes the transition. The path to override the latch PFET-feedback must have an impedance less than that of the PFET, and the transition must occur before the wordline device is deactivated at the end of the write operation.
FIG. 4
shows the write operation with different bitline contact resistances of RC=5&OHgr;, RC=10 K&OHgr;, and RC=15 K&OHgr;. As shown in
FIG. 4
, the cell nodes A and B fail to be written when RC is greater than 15 K&OHgr; at nominal conditions. At 15 K&OHgr;, the cell nodes are written, but with very little margin to the falling edge of the wordline. Thus, the threshold of detectability of resistive bitline contacts is more critical during a write operation, compared to a read operation by approximately 2×. An inability to detect and screen out bitline contacts with resistances approaching 20 K&OHgr; (4,000 times greater than nominal) will lead to shipments of SRAMs with highly resistive, potentially unreliable bitline contacts.
One alternative that improves the detectability of resistive contacts is to shorten the width of the wordline by speeding up the falling edge of the wordline pulse. Referring back to
FIG. 4
, if the falling edge of the wordline is sped up by approximately 400 ps then the write of the

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