DRAM with reduced-test-time-mode

Details DRAM with reduced-test-time-mode DRAM with reduced-test-time-mode

1991-08-22

1994-09-06

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

36518901, 365226, 36518911, 371 212, G11C 700, G11C 2900

Patent

active

RE0347183

ABSTRACT:
In a semiconductor memory device comprising a plurality of memory cells, a test request detection circuit responds to a voltage, on an input terminal, higher than a range of voltages supplied under ordinary operation condition for producing a test signal. Responsive to the test signal, data which has been supplied to the semiconductor memory device are simultaneously written into a plurality of memory cells, and data are simultaneously read from a plurality of memory cells, and judgement is made as to whether or not the data from the memory cells coincide with the data originally supplied to the semiconductor memory device.

REFERENCES:
patent: 4055754 (1977-10-01), Chesley
patent: 4495603 (1985-01-01), Varshney
patent: 4541090 (1985-09-01), Shiragasawa
patent: 4543647 (1985-09-01), Yashida
patent: 4612630 (1986-09-01), Rosier
patent: 4651304 (1987-03-01), Takata
patent: 4654849 (1987-03-01), White, Jr. et al.
patent: 4672583 (1987-06-01), Nakaizami
patent: 4686456 (1987-08-01), Furuyama et al.
M. T. Swarakowski, "Redundant Clock Magnetic Recording", vol. 12, No. 2, Jul. 1969, p. 254.
Inoue et al., "An 85ns 1Mb DRAM in a Plastic DIP", ISCC 85, pp. 238-239, Feb. 15, 1985.
Kumanoya et al., "A 90ns 1Mb DRAM with Multi-Bit Test Mode", ISSCC 85, pp. 240-241, Feb. 15, 1985.
R. C. Cady et al., "RAM Internal Parallel Testing Technique", IBM TDB, vol. 27, No. 7B, Dec. 1984, pp. 4534-4536.
Abstract, System for Updating and Controlling Main Key, T. Chiba, Fujitsu K.K.; Appl. No. 57-31326, Feb. 27, 1982.
Abstract: System for ControlLing Memory, M. Matsumto, Fujitsu K.K.; Appl. No. 57-33414, Mar. 3, 1982.
Abstract: System for Checking Memory, M. Wakabayashi, USAC Denshi Kogyo K.K.; Appl. No. 57-33550, Mar. 3, 1982.
Abstract: Semiconductor Storage Device, J. Inoue, Nippon Denshin Denwa Kosha; Appl. No. 56-62424, Apr. 27, 1981.
Abstract: Semiconductor Memory, M. Ishikawa, Tokyo Shibaura Denki K.K.; Appl. No. 56-63004, Apr. 25, 1981.
Abstract: Memory Device Having Redundancy, S. Saitou, Tokyo Shibaura Denki K.K.; Appl. No. 57-179998, Apr. 25, 1981.
Abstract: IC Card, K. Hatsutori, Nippon Denshin Denwa Kosha; Appl. No. 57215474, Dec. 10, 1982.
Abstract: Data Checking Method of Electronic Memory, K. Tanaka; Appl. No. 57-215998, Dec. 8, 1982.
Abstract: EPROM Memory Device with Test Circuit, A. Takada; Appl. No. 57-216346, Dec. 9, 1982.
Abstract: Memory Control System, K. Furukawai, Appl. No. 56-205303, Dec. 21, 1981.
Abstract: Controller for Plural Storage Parts in Data Processing System, Y. Chiwaki, Nippon Denki K.K.; Appl. No. 56-71471, May 14, 1981.
Abstract: Semiconductor Storage Device, M. Satou, Tokyo Shibaura Denki K.K., Tokyo Shibaura Denki K.K.; Appl. No. 56-72613, May 14, 1981.

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