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CMOS device structure with reduced short channel effect and memo

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent

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CMOS device structures and method of making same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device with deep current path for ESD protection

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent

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CMOS device with dual-epi channels and self-aligned contacts

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device with metal and silicide gate electrodes and a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device with raised source and drain regions

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS devices having dual high-mobility channels

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS devices with a single work function gate electrode and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS devices with balanced drive currents based on SiGe

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS devices with different metals in gate electrodes using...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS devices with hybrid channel orientations and method for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS devices with improved gap-filling

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS fabrication

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS gate electrode using selective growth and a fabrication...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS gate structure comprising predoped semiconductor gate...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS gate structure comprising predoped semiconductor gate...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS image sensor and fabricating method thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS image sensor and manufacturing method thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS image sensor and method for fabricating the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS image sensor and method for fabricating the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Charge transfer device
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