CMOS devices with improved gap-filling

Details CMOS devices with improved gap-filling CMOS devices with improved gap-filling

2006-03-30

2008-05-27

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000, C438S981000, C257SE21640

Reexamination Certificate

active

07378308

ABSTRACT:
A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the second MOS device includes a second spacer liner. A first stressed film having a first thickness is formed over the first MOS device and directly on the first spacer liner. A second stressed film having a second thickness is formed over the second MOS device and directly on the second spacer liner. The first and the second stressed films may be formed of a same material.

REFERENCES:
patent: 6156598 (2000-12-01), Zhou et al.
patent: 6849546 (2005-02-01), Tu et al.
patent: 7220630 (2007-05-01), Cheng et al.
patent: 2006/0157795 (2006-07-01), Chen et al.
Nakahara et al., “A Robust 65-nm Node CMOS Technology for Wide-range Vdd Operation”, 2003 IEEE, pp. 11.2.1-11.2.4.

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