Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-04-15
2004-02-24
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S212000, C438S216000, C438S270000, C438S299000, C438S674000, C438S933000, C257S369000, C257S377000, C257S410000, C257S412000
Reexamination Certificate
active
06696328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof. More particularly, the present invention relates to a gate pattern of a CMOS transistor that uses polysilicon germanium (poly-SiGe) as a gate electrode, and a fabrication method thereof.
2. Description of the Related Art
As semiconductor devices have been developed to be highly integrated, operate at high speed, and consume less power, scaling down of complementary metal oxide semiconductor (CMOS) transistors in semiconductor devices has been rapidly achieved. This scaling down, however, causes a short channel effect in the CMOS transistors. In order to suppress the short channel effect, a dual gate type CMOS transistor, in which a surface channel, symmetrical gate patterns, and a low-voltage threshold voltage Vth can be formed, is extensively used.
Conventionally, a dual gate type CMOS transistor is fabricated by depositing a polysilicon layer for a gate electrode on a semiconductor substrate, ion-implanting N-type impurities, such as phosphorous or arsenic, into an NMOS region and P-type impurities, such as boron, into a PMOS region.
However, the above conventional manufacturing method is disadvantageous in that it is difficult to precisely control the threshold voltage Vth of a gate pattern, and the characteristics of a PMOS element deteriorate because the thickness of a gate oxide layer is 50 Å or less, a poly gate depletion effect caused by penetration of a boron ion into a PMOS region appears, and the threshold voltage Vth is unstable.
To cope with the poly gate depletion effect, it has been suggested that a gate electrode be used with a polysilicon germanium layer instead of a polysilicon layer. Using the polysilicon germanium layer as the gate electrode makes it possible to use the conventional manufacturing method and suppresses the penetration of a boron ion into the PMOS region, thereby preventing an occurrence of the poly gate depletion effect. Further, an increase in the threshold voltage Vth due to a difference in work functions results in channel doping, thus improving current drivability due to an increase in carrier mobility.
The characteristics of a CMOS transistor that adopts a gate electrode of a polysilicon germanium layer, however, deteriorate in an NMOS region, unlike in the PMOS region. This is because polysilicon germanium has low solubility and a low deactivation rate with respect to phosphorous (P) or arsenic (Ar) as compared to polysilicon. For this reason, the thicker the density of germanium in the polysilicon germanium is, the more the poly gate depletion effect increases.
Therefore, if a polysilicon germanium layer is used as a gate electrode in the dual gate type CMOS transistor, the characteristics of the CMOS transistor are enhanced in the PMOS region but are reduced in the NMOS region, thereby preventing an improvement in the overall characteristics of the CMOS transistor.
In conclusion, a CMOS transistor having a gate electrode of a polysilicon germanium layer is conventionally fabricated by depositing a polysilicon germanium layer throughout PMOS and NMOS regions in a semiconductor substrate, and ion-implanting P-type and N-type impurities into the PMOS region and the NMOS region, respectively. Accordingly, in the resultant CMOS transistor, it is difficult to form a gate electrode of a different material, which is not P-type or N-type impurities, in the PMOS region and the NMOS region.
SUMMARY OF THE INVENTION
In an effort to solve the above problem, it is a first feature of an embodiment of the present invention to provide a method of manufacturing a CMOS gate electrode, in which polysilicon germanium is used as a material for a gate electrode in a PMOS region and polysilicon is used as a material for a gate electrode in an NMOS region, and also uses selective growth to prevent deterioration of overall CMOS transistor characteristics.
It is a second feature of an embodiment of the present invention to provide a CMOS gate electrode obtained using such a method.
To provide one aspect of the first feature of an embodiment of the present invention, there is provided a method of fabricating a CMOS gate electrode using a selective growth method, including (a) sequentially forming a gate oxide layer, a first polysilicon layer, and polysilicon germanium (poly-SiGe) layer on a semiconductor substrate in which an NMOS region and a PMOS region are defined by an isolation layer; (b) forming a hard mask layer on the PMOS region; (c) selectively removing the poly-SiGe layer from the NMOS region using the hard mask layer so as to expose the first polysilicon layer on the NMOS region; (d) selectively growing the exposed first polysilicon layer on the NMOS region so as to form a second polysilicon layer only on the NMOS region; (e) ion-implanting N-type impurities into the NMOS region, using the hard mask layer as an ion-implanting mask; (f) removing the hard mask layer; and (g) patterning the resultant structure to form first and second gate stacks on the PMOS region and the NMOS region, respectively.
Preferably, the isolation layer is a trench isolation layer, the first polysilicon layer is formed to a thickness in a range of about 50-500 Å, the poly-SiGe layer contains germanium in a concentration greater than about 20% and more preferably, in a concentration in a range of about 20-99%, and the first polysilicon layer and the poly-SiGe layer are formed in-situ in the same chamber.
Also preferably, the hard mask is a nitride layer, selectively removing the poly-SiGe layer is performed by wet etching, a mixture of NH
4
OH, H
2
O, and H
2
O
2
is used as an etching solution during the wet etching, and selectively growing the second polysilicon layer is performed at a temperature in a range of about 500-850° C., using a gas containing silicon and an HCI gas.
Preferably, the method may further include after removing the hard mask layer, depositing a third polysilicon layer for forming a silicide layer on a top surface of the resultant structure. In addition, the method may further include forming gate spacers, which are preferably nitride layers, along sidewalls of the first and second gate stacks after forming the first and second gate stacks.
To provide another aspect of the first feature of an embodiment of the present invention, there is provided a method for manufacturing a CMOS gate electrode using a selective growth method, including (a) sequentially forming a gate oxide layer and a polysilicon germanium (poly-SiGe) layer on a semiconductor substrate in which an NMOS region and a PMOS region are defined by an isolation layer; (b) forming a hard mask layer on the PMOS region; (c) selectively etching a portion of the poly-SiGe layer from the NMOS region using the hard mask layer; (d) selectively growing the poly-SiGe layer that remains on the NMOS region to form a first polysilicon layer; (e) ion-implanting N-type impurities into only the NMOS region using the hard mask layer as an ion-implanting mask; (f) removing the hard mask layer; and (g) patterning the resultant structure to form a first gate stack on the PMOS region and the second gate stack on the NMOS region.
Preferably, the poly-SiGe layer contains germanium in a concentration greater than about 20% and more preferable, in a range of about 20-99%, and when selectively etching a portion of the poly-SiGe layer on the NMOS region, the poly-SiGe layer, which remains on the NMOS region, is etched to have a thickness in a range of about 50-500 Å.
Preferably, the method may further include depositing a second polysilicon layer on a top surface of the resultant structure after removing the hard mask layer, and forming gate spacers, which are preferably nitride layers, along sidewalls of the first and second gate stacks after patterning the resultant structure.
To provide one aspect of the second feature of an embodiment of the present invention, there is provided a CMOS gate electrode fabricated by a selective growth method, including a sem
Bae Geum-jong
Ha Young-ki
Kim Ki-chul
Kim Sang-su
Lee Jung-il
Lee & Sterba, P.C.
Picardat Kevin M.
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