CMOS fabrication

Details CMOS fabrication CMOS fabrication

2005-06-14

2010-12-28

Toledo, Fernando L (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S546000, C438S551000, C438S555000, C438S671000, C438S717000, C438S736000, C257SE21023, C257SE21037, C257SE21038, C257SE21232, C257SE21246, C257SE21257, C257SE21434, C257SE21474

Reexamination Certificate

active

07858458

ABSTRACT:
A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.

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