LandOfFree - US Patents - Listing for Error detection/correction and fault detection/recovery,Pulse or data error handling

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Test vector generating method and test vector generating...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Test vehicle data analysis

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Test vehicle data analysis

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Test wrapper including integrated scan chain for testing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Test-facilitating circuit for information processing devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Testability architecture for modularized integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing

Testable bus control logic circuitry and method for using same

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Testable circuit with a low number of leads

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Testable design methodology for clock domain crossing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Testable IC having analog and digital circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Testable integrated circuit, integrated circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Testable interleaved dual-DRAM architecture for a video memory c

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Testable programmable gate array and associated LSSD/determinist

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment

Testable read-only memory for data memory redundant logic

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Testable transparent latch and method for testing logic...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate

Testable up down counter for use in a logic analyzer

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Tester and method for testing LSI designed for scan method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Tester architecture construction data generating method,...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Tester arrangement comprising a connection module for testing, b