Testable read-only memory for data memory redundant logic

Details Testable read-only memory for data memory redundant logic Testable read-only memory for data memory redundant logic

2000-02-08

2003-03-18

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S719000, C365S201000

Reexamination Certificate

active

06536003

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a testable read-only memory for data memory redundant logic for the storage of fault addresses, determined in a test procedure, of faulty data memory units within a main data memory.
The increasing memory requirement for application programs has led to the memory sizes of semiconductor memories having increased greatly in recent years. With the increase in memory size, and the concomitant increased integration level, in the production of semiconductor memories, there is an increase in the probability of individual data memory units in the semiconductor memory being produced with faults in the production process, and thus being unfit for use. In order that the failure of isolated data memory units does not lead to the entire semiconductor memory becoming unserviceable or defective, redundant memory areas are increasingly being installed in data memories. Such redundant memories contain a redundant address memory with a plurality of redundant address memory units, as well as a redundant data memory with redundant data memory units. Each redundant address memory unit has an associated redundant data memory unit.
If a faulty data memory unit is found within the main data memory during a test process, the fault address for the faulty data memory unit is written to an address memory unit in the redundant address memory and, when data access is made to this fault address, the associated data memory unit within the redundant data memory is accessed rather than the faulty data memory unit within the main data memory.
This readdressing process allows a certain number of faulty data memory units within the main data memory to be replaced by redundant data memory units within the redundant data memory.
The access to the redundant address memory and to the redundant data memory is controlled by redundant control logic that is integrated in the data memory. The redundant address memory within the redundant control logic is formed by address registers which, if the power supply fails, lead to the loss of the fault addresses stored in them for faulty data memory units within the main data memory.
The fault addresses of faulty data memory units determined in the test process are thus additionally permanently programmed into a read-only memory, in which case the fault addresses in this memory are written once again, if required, to the redundant address memory. The read-only memories in this case comprise a large number of read-only memory units, which permanently store the address BITs of the fault addresses.
Reference is now had to
FIG. 1
, which shows a read-only memory unit according to the prior art. The read-only memory unit contains a fuse link device F, to which a BIT, for example an address BIT, can be written permanently, i.e., non-erasably. As a rule, the fuse link device F comprises a fusible resistor, which is composed of metal or polysilicon.
When a control signal is applied to a write terminal W a P-channel MOSFET P
1
that is connected to the supply voltage VDD is switched through, so that a potential node P can be precharged in order to precharge the fuse link device F.
The BIT written to the fuse link device F can be read by application of a read signal R to the gate of the MOSFET T
2
, which is complementary to the first MOSFET.
Application of a control signal GND to the transistor T
3
results in the data value written in the fuse link device being drawn to ground, and thus becoming logic 0.
A latch circuit which comprises two feedback inverter circuits I
1
, I
2
is connected downstream of the potential node P. A data output buffer A is connected downstream of the latch circuit. The data output buffer A likewise comprises an inverter.
The BIT read from the fuse link device F is applied to the output DA of the output buffer A when a read control command is applied to the terminal R.
The read-only memory unit shown in
FIG. 1
has the disadvantage that its own serviceability cannot be tested.
If a circuitry fault occurs during the process of producing the read-only memory, an incorrect logic value may in some circumstances be present at the output DA of the read-only memory unit.
For example, in the event of a power failure and the subsequent writing of the fault addresses from the read-only memory, an incorrect address will be written to the redundant address memory in the redundant control logic. The readdressing of a faulty data memory unit within the main data memory to a redundant data memory unit within the redundant data memory will then be permanently faulty.
SUMMARY OF THE INVENTION
The object of the invention is to provide a testable read-only memory for data memory redundant logic which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which allows checking for serviceability by means of a test process.
With the above and other objects in view there is provided, in accordance with the invention, a testable read-only memory for data memory redundant logic, comprising:
a plurality of read-only memory units for storing determined fault addresses of faulty data memory units, wherein a serviceability of each the read-only memory unit can be checked by application of input test data and by comparison of read output test data with expected nominal output test data.
In other words, the objects of the invention are satisfied with the testable read-only memory for data memory redundant logic having read-only memory units for storage of determined fault addresses of faulty data memory units, in which the serviceability, i.e., the functionality, of each read-only memory unit can be checked by application of input test data and by comparison of read output test data with expected nominal output test data.
In accordance with an added feature of the invention, each read-only memory unit stores one address BIT of a fault address.
In accordance with an additional feature of the invention, the read-only memory is switchable between a test mode and a normal mode.
In accordance with another feature of the invention, the read-only memory units comprise a fuse link device for non-erasable writing of an address BIT. Preferably, the fuse link device is a fusible resistor composed of metal or polysilicon.
In accordance with a further feature of the invention, the read-only memory unit has a read circuit for reading a written address BIT.
In accordance with again an added feature of the invention, a latch circuit with two feedback inverters is connected downstream of the read circuit.
In accordance with again an additional feature of the invention, the latch circuit includes a multiplexer.
In that case, the multiplexer preferably includes a control terminal for switching between a test mode and a normal mode.
In accordance with again another feature of the invention, the multiplexer includes a first data input for application of test data.
In accordance with again a further feature of the invention, the latch circuit includes a first inverter with an output, and the multiplexer has a second data input connected to the output of the first inverter.
In accordance with yet an added feature of the invention, the latch circuit includes a second inverter with an input, and the multiplexer has an output connected to the input of the second inverter.
In accordance with yet an additional feature of the invention, a data output buffer is connected to the second data input of the multiplexer and to the output of the first inverter.
In accordance with yet another feature of the invention, a serial shift register with a sampling flip-flop is provided, and the data output buffer outputs the data to the sampling flip-flop in the serial shift register.
In accordance with yet a further feature of the invention, a data output of the sampling flip-flop is connected to the first data input of the multiplexer for application of test data.
In accordance with yet again an added feature of the invention, there is provided a redundant control logic in a data memory, the data me

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