Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-05
2002-05-21
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S726000, C714S733000, C324S1540PB, C324S755090, C324S763010
Reexamination Certificate
active
06393593
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to LSI testers and, more particularly, to a LSI tester for executing a DC test and a function test of a semiconductor integrated circuit.
2. Description of the Related Art
FIG. 6
shows a construction of a LSI tester according to the related art. Referring to
FIG. 6
, the LSI tester comprises tester pins
90
-
1
through
90
-n connected to respective input/output pins of a semiconductor integrated circuit, a DC test device
4
for testing the semiconductor integrated circuit to determine its dc characteristic by applying a preset voltage to the tester pins
90
-
1
through
90
-n, and function test devices
80
-
1
through
80
-n for determining the function of the semiconductor integrated circuit by applying a voltage corresponding to a test pattern for a function test and receiving, via the tester pins
90
-
1
through
90
-n, corresponding logic values returned from the semiconductor integrated circuit as a result of the application of the voltage.
The function test devices
80
-
1
through
80
-n respectively comprise function test execution units
8
-
1
through
8
-n for generating the test pattern for a function test and determining the function of the semiconductor integrated circuit. There are further provided input/output units
9
-
1
through
9
-n for applying the voltage generated by the function test execution units
8
-
1
through
8
-n to the tester pins
90
-
1
through
90
-n, respectively, and supplying, to the function test execution units
8
-
1
through
8
-n, respectively, the logic values returned from the semiconductor integrated circuit as a result of the application of the voltage and received via the tester pins
90
-
1
through
90
-n, respectively.
The LSI tester also includes switches
100
-
1
through
100
-n for connecting the dc test device
4
to the tester pins
90
-
1
through
90
-n, respectively, in a dc test, switches
200
-
1
through
200
-n for connecting the function test devices
80
-
1
through
80
-n to the tester pins
90
-
1
through
90
-n, respectively, in a function test, and a controller
16
for controlling the dc test device
4
, the function test devices
80
-
1
through
80
-n, the switches
100
-
1
through
100
-n and the switches
200
-
1
through
200
-n.
A description will now be given of the operation of the LSI tester according to the related art.
Recently, many semiconductor integrated circuits have a built-in scan circuit or a boundary scan circuit to facilitate a function test.
A semiconductor integrated circuit may have a large number of input/output pins. However, if the circuit is designed for the scan method, a test can be performed by applying a test pattern voltage to small number of (normally, no more than 10) input/output pins.
In a dc test, the controller
16
turns the switches
100
-
1
through
100
-n on and the switches
200
-
1
through
200
-n off so as to connect the dc test device
4
to the tester pins
90
-
1
through
90
-n.
Under the control of the controller
16
, the dc test device
4
tests the semiconductor integrated circuit to determine its dc characteristic by applying the preset voltage to the tester pins
90
-
1
through
90
-n.
A voltage greater than 3V (for example, 3.3V) may be applied to the test pins
90
-
1
through
90
-n. A measurement is made to determine if a current is output from the input/output pins of the semiconductor integrated circuit. If a current is not output, it is determined that the circuit is normal.
In a function test, the controller
16
turns the switches
100
-
1
through
100
-n off and the switches
200
-
1
through
200
-n on so as to connect the function test devices
80
-
1
through
80
-n to the tester pins
90
-
1
through
90
-n, respectively.
Under the control of the controller
16
, each of the function test execution units
8
-
1
through
8
-n of the respective function test devices
80
-
1
through
80
-n generates a test pattern for a function test. The input/output units
9
-
1
through
9
-n of the respective function test devices
80
-
1
through
80
-n apply the voltage corresponding to the test pattern to the respective test pins
90
-
1
through
90
-n, respectively.
When the voltage corresponding to the test pattern is applied to the test pins
90
-
1
through
90
-n and consequently to the corresponding input/output pins of the semiconductor integrated circuit, the semiconductor integrated circuit performs corresponding logic operations responsive to the input of the test patterns. The results of the logic operations are output to the input/output pins of the circuit. The input/output units
9
-
1
through
9
-n of the respective function test devices
80
-
1
through
80
-n receive the results via the tester pins
90
-
1
through
90
-n, respectively, and supply the received results to the function test execution units
8
-
1
through
8
-n, respectively.
Upon receipt of the results from the semiconductor integrated circuit, each of the function test execution units
8
-
1
through
8
-n of the respective function test devices
80
-
1
through
80
-n compares the result with an expectation value corresponding to the test pattern to determine whether the semiconductor integrated circuit is operating properly.
Notwithstanding its capability of executing both a dc test and a function test of a semiconductor integrated circuit, the related-art LSI tester constructed as described above has a drawback in that the production cost is high because it is not only necessary to provide tester pins but also an equal number of function test devices that are relatively expensive. The price of a LSI tester is generally determined by the number of function test devices.
SUMMARY OF THE INVENTION
Accordingly, a general object of the present invention is to provide a LSI tester in which the aforementioned drawback is eliminated.
Another and more specific object of the present invention is to provide a LSI tester in which a function test device is shared so that the production cost is reduced.
The aforementioned objects can be achieved by a LSI tester comprising: a plurality of tester pins each connected to an input/output pin of a semiconductor integrated circuit; a plurality of dc test devices each applying one of a predetermined voltage and a predetermined current to a corresponding one of the plurality of tester pins so as to determine a dc characteristic of the semiconductor integrated circuit; a function test device for determining a function of the semiconductor integrated circuit by applying a voltage corresponding to a function test pattern to selected ones of the plurality of tester pins and receiving, via the selected ones of the plurality of tester pins, corresponding logic values returned from the semiconductor integrated circuit as a result of the application of the voltage; and connecting means for connecting, in the dc test, the plurality of dc test devices to the plurality of tester pins, respectively, and connecting, in the function test, the function test device to the selected ones of the plurality of tester pins.
The aforementioned objects can also be achieved by a LSI tester comprising: a plurality of tester pins each connected to an input/output pin of a semiconductor integrated circuit; a plurality of dc test devices each applying one of a predetermined voltage and a predetermined current to a corresponding one of the plurality of tester pins so as to determine a dc characteristic of the semiconductor integrated circuit; function test execution means for generating a voltage corresponding to a function test pattern and determining a function of the semiconductor integrated circuit; a plurality of input/output means each applying a voltage corresponding to the test pattern generated by the function test execution means to a corresponding one of the plurality of tester pins, and supplying, to the function test executing means, a corresponding logic value returned from the semiconductor integrated circuit as a result of the application
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